1
NT68P81
USB Keyboard Micro-Controller
V2.2
NT68P81
2003/2/24 2 Ver2.2
1 REVISION
HISTORY ...................................................................................................................... 4
2 FEATURES
.................................................................................................................................... 5
3 GENERAL
DESCRIPTION ............................................................................................................. 5
4 PIN
CONFIGURATION ................................................................................................................... 5
5 PAD
CONFIGURATION.................................................................................................................. 6
6 BLOCK
DIAGRAM ......................................................................................................................... 7
7 PIN AND PAD DESCRIPTIONS ..................................................................................................... 8
8 FUNCTIONAL
DESCRIPTION
....................................................................................................... 9
8.1 6502CPU ............................................................................................................................... 9
8.2 INSTRUCTION SET LIST .................................................................................................... 10
8.3 OTP ROM ............................................................................................................................ 12
8.4 SRAM .................................................................................................................................. 17
8.5 SYSTEM RESERVED REGISTERS .................................................................................... 18
8.6 POWER-ON RESET ............................................................................................................ 18
8.7 TIMING GENERATOR......................................................................................................... 18
8.8 BASE TIMER (BT) ............................................................................................................... 19
8.9 INTERRUPT CONTROLLER ............................................................................................... 20
8.9.1 TIMER INTERRUPT ............................................................................................................ 20
8.9.2 INT0 INTERRUPT ............................................................................................................... 20
8.9.3 INT1 INTERRUPT ............................................................................................................... 20
8.9.4 KBD INTERRUPT ............................................................................................................... 20
8.9.5 IN0 TOKEN INTERRUPT .................................................................................................... 20
8.9.6 OT0 (OUT0) TOKEN INTERRUPT ...................................................................................... 20
8.9.7 IN1 TOKEN INTERRUPT .................................................................................................... 21
8.9.8 IN2 TOKEN INTERRUPT .................................................................................................... 21
NT68P81
2003/2/24 3 Ver2.2
8.9.9 STUP (SETUP) TOKEN INTERRUPT ................................................................................. 21
8.9.10 SUSP INTERRUPT............................................................................................................ 21
8.10 I/O PORTS ......................................................................................................................... 21
8.11 WATCH-DOG TIMER (WDT).............................................................................................. 22
8.12 POWER CONTROL ........................................................................................................... 22
8.13 UNIVERSAL SERIAL BUS INTERFACE............................................................................ 22
8.14 SUSPEND AND RESUME.................................................................................................. 22
8.15 RESET SOURCE SUMMERY ............................................................................................ 23
8.16 PS/2 MOUSE APPLICATION............................................................................................. 23
9 ABSOLUTE
MAXIMUM
RATING.................................................................................................. 24
10 DC ELECTRICAL CHARACTERISTICS ....................................................................................... 24
11 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 25
12 APPLICATION CIRCUIT 1 (SIMPLE KEYBOARD WITH PS/2 MOUSE) ..................................... 26
13 APPLICATION CIRCUIT 2 (WINDOWS 2000 COMPATIBLE KEYBOARD) ................................ 27
14 APPLICATION CIRCUIT 3 (MINI KEYBOARD)............................................................................ 28
11 BONDING DIAGRAM ................................................................................................................... 30
12 ORDERING INFORMATION ........................................................................................................ 31
13 PACKAGE INFORMATION ......................................................................................................... 32
NT68P81
2003/2/24 4 Ver2.2
Revision History
NT68P81 Specification Revision History
Version Content Data
2.2
1. Application circuit 1, 2 and 3 add 0.1uF to
RESET
(Page
26, 27 and 28)
2. Substrate connect to GND (Page 30)
3. Code number modified (Page 31)
Feb. 2003
2.1
1. FN Key Model Usage for Consumer Keys modified -
FN_K22 and FN_K24 (Page 24)
Oct. 2002
2.0
1. Volume Knob Application deleted (Page 18)
2. PS/2 Mouse Application added (Page 18 and 19)
3. Application circuit 2 and 3 modified (Page 22 and 23)
4. FN key usage added (Page 24)
5. Standard code functional descriptions modified (Page
26)
Sep. 2002
1.3
1. Application circuits modified (Page 20, 21 and 22)
2. Standard code functional description added (Page 24)
July 2002
1.0 Original
Nov.
1998
NT68P81
2003/2/24 5 Ver2.2
Features
!
Built-in 6502C 8-bit CPU
!
3 MHz CPU operation frequency when oscillator is running at 6 MHz
!
6K bytes of OTP (one time programming) ROM
! 256 bytes of SRAM
!
One 8-bit programmable base timer with pre-divider circuit
!
29 programmable bi-directional I/O pins including two external interrupts
!
3 LED direct sink pins with internal serial resistors
!
On-chip oscillator (Crystal or Ceramic Resonator)
!
Watch-dog timer reset
!
Built-in power-on reset
!
USB interface
!
3 supported endpoints
!
Remote wakeup provided
!
CMOS technology for low power consumption
!
40-pin DIP package, 42-pad Dice form and COB
General Description
The NT68P81 is a single chip micro-controller for USB keyboard applications. It incorporates a 6502C 8-bit CPU core, 6K
bytes of OTP ROM, and 256 bytes of RAM used as working RAM and stack area. It also includes 29 programmable bi-
directional I/O pins with built-in resistors, and one 8-bit pre-loadable base timer. Additionally, it includes a built-in power-on
reset, a built-in low voltage reset, an oscillator that requires crystal or ceramic resonator applied, and a watch-dog timer that
prevents system standstill.
Pin Configuration
GND
VCP
VDP
VDM
[OE] P30
[PGM] P31
INT0/P32
INT1/P33
P34
[A9] P11
[A0] P00
[A2] P02
[A3] P03
P17
[A4] P04
P20 [DB0]
P21 [DB1]
P22 [DB2]
P23 [DB3]
P25 [DB5]
P26 [DB6]
LED0 [MODE0]
LED1 [MODE1]
V
DD
LED2 [MODE2]
OSCO
OSCI
P12 [A10]
P27 [DB7]
NT68P81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
[VPP] RESET
[A1] P01
[A5] P05
[A6] P06
[A7] P07
[A8] P10
17
18
19
20
P24 [DB4]
P16
P15 [CE]
P14 [A12]
P13 [A11]
24
23
22
21
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