NT7181
V 2.1
LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface
NT7181 Specification
V 2.1
NOVATEK MICROELECTRONICS CORP.
1
1 FEATURES
....................................................................................................................................................................... 3
2 GENERAL
DESCRIPTION ............................................................................................................................................ 3
2.1 B
LOCK
D
IAGRAMS
....................................................................................................................................................... 3
3 PIN
CONFIGURATION .................................................................................................................................................. 4
4
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................. 5
4.1 R
ECOMMENDED
O
PERATING
C
ONDITIONS
.................................................................................................................... 5
4.2 T
IMING
R
EQUIREMENTS
............................................................................................................................................... 5
5
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS......................... 6
6
SWING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS .................................... 7
7 PARAMETER
MEASUREMENT INFORMATION.................................................................................................... 8
8 APPLICATION
INFORMATION
............................................................................................................................... 12
9 ORDERING
INFORMATION
..................................................................................................................................... 14
10 PACKAGE
INFORMATION
....................................................................................................................................... 15
2
1 Features
!
28:4 Data Channel Compression at up to 297 Megabytes
per Second Throughput
!
Suited for VGA, SVGA, XGA and Dual pixel SXGA,
UXGA Display Data Transmission From Controller to
Display With Very Low EMI
!
28 Data Channels and Clock-In Low-Voltage TTL and 4
Data Channels and Clock-Out Low-Voltage Differential
!
Operates From a Single 3.3V Supply With 250mW (Typ)
!
Low profile 56 Lead TSSOP Package
!
Clock edge Programmable for Transmitter
!
Wide Phase-Lock Input Frequency Range: 25 MHz To
85 MHz
!
Supports Spread Spectrum Clock Generator
!
Suggests to use for LCD monitor only
!
No External Components Required for PLL
2 General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage
differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL)
data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the
DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable edge data strobes for convenient
interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for rising edge strobe(RFB=1) or
falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the
NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times
and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock
(TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the
transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the
possible use of the shutdown/clear (
PWDN
) active-low input to inhibit the clock and shut off the LVDS output drivers for
lower power consumption. A low level on this signal clears all internal registers to a low level.
The NT7181 are characterized for operation over free-air temperature ranges of 0
C to 70
C.
2.1 Block Diagrams
T
T
L
P
A
R
A
L
L
E
L
|
T
O
|
L
V
D
S
PLL
CMOS / TTL INPUTS
DATA (LVDS)
CLOCK (LVDS)
(25 MHz To 85 MHz)
TD0-6
TD7-13
TD14-20
(TRANSMIT CLOCK IN)
(25 MHz To 85 MHz)
POWER DOWN
(175 Mbit/s To 595 Mbit/s On
Each LVDS
Cnannel)
NT7181
7
7
7
T0P
T0M
T1P
T1M
T2P
T2M
TCLKP
TCLKM
TD21-27
7
T3M
T3P
3
3 Pin Configuration
NT7181
VCC
TD11
TD12
TD13
GND
TD14
TD15
TD16
RFB
TD17
TD18
TD19
GND
TD20
TD21
PLLGND
TD22
PLLVCC
PWDN
LVDSGND
T3P
TCLKP
T2M
LVDSGND
LVDSVCC
T1M
T0P
T0M
T2P
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TCLKM
T3M
T1P
3
4
5
6
7
8
1
2
VCC
TD5
TD6
TD7
GND
TD8
TD9
TD10
49
50
51
52
53
54
55
56
TD4
TD3
TD2
GND
TD1
TD0
TD27
LVDSGND
25
27
26
28
31
32
30
29
TD23
VCC
TD24
TD25
TD26
CLKIN
GND
PLLGND
4
4 Absolute Maximum Ratings
Supply voltage range, V
CC
(see Note1)..............................................................-0.3V to 4V
Output voltage range, V
O.....
............................................................................-0.3V to V
CC
+0.3V
Input voltage range, V
I.....................................
..........................................................-0.3V to Vcc +0.3V
Storage temperature range, Tstg.....................................................................-65
C to 150
C
Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds...........................260
C
Junction Temperature....................................................................................150
C
#
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress
ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of
this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect
device reliability.
4.1 Recommended Operating Conditions
Symbol Parameter
Min.
Nom.
Max.
Unit
VCC Supply
voltage
3.0
3.3
3.6
V
V
IH
High-level input voltage
2
V
V
IL
Low-level input voltage
0.8
V
Z
L
Differential load impedance
90
100
110
T
A
Operating
free-air
temperature 0
70
C
4.2 Timing requirements
Symbol Parameter Min.
Nom.
Max.
Unit
T
C
Cycle time, input clock
11.8
40
ns
t
W
Pulse duration, high-level input clock
0.4t
c
0.6t
c
ns
t
T
Transition,
5
ns
t
su
Setup time, data, TD0 - TD27 valid before CLKIN
or CLKIN
(See Figure 1)
5 ns
t
h
Hold time, data, , TD0 - TD27 valid after CLKIN
or CLKIN
(See Figure 1)
2.5 ns
Note:
t
h
is measured under the conditions of input clock jitter of 1.9ns at 65MHz.
5
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