NT7704
240 Output LCD Segment/Common Driver
1
V1.0
Features
(Segment mode)
!
Shift Clock frequency:
20 MHz (Max.) (V
DD
= 5 V
10%)
12 MHz (Max.) (V
DD
= 2.5V - 4.5V)
!
Adopts a data bus system
!
4-bit/8-bit parallel input modes are selectable with a
mode (MD) pin
!
Automatic transfer function with an enable signal
!
Automatic counting function when in "chip select" mode,
which causes the internal clock to be stopped by
automatically counting 240 bits of input data
(Common mode)
!
Shift clock frequency :
4.0 MHz (Max.)
!
Built-in 240-bits bidirectional shift register (divisible into
120-bits x 2)
!
Available in a single mode (240-bits shift register) or in a
dual mode(120-bits shift register x 2)
1. Y1
Y240
Single mode
2. Y240
Y1
Single mode
3. Y1
Y120, Y121
Y240
Dual mode
4. Y240
Y121, Y120
Y1
Dual mode
The above 4 shift directions are pin-selectable
(Both for segment mode and common mode)
!
Supply voltage for LCD driver: 15.0 to 30.0 V
!
Number of LCD driver outputs: 240
!
Low output impedance
!
Low power consumption
!
Supply voltage for the logic system: +2.5 to +5.5 V
!
COMS process
!
Package: Gold bump die / 272 Pin TCP(Tape Carrier
Package)
!
Not designed or rated as radiation hardened
General Description
The NT7704 is a 240-bit output segment/common driver LSI
suitable for driving large scale dot matrix LCD panels used
by PDA's, personal computers and work stations for
example. Through the use of COG technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7704 is good as both a segment driver
and as a common driver, and a low power consuming, high-
precision LCD panel display can be assembled using the
NT7704. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In the common mode, the data input/output
pins are bi-directional and the four data shift directions are
pin-selectable.
Pin Configuration
NT7704
33
151
Y
1
2
3
Y
1
2
2
Y
1
2
1
Y
1
2
0
Y
1
1
9
Y
1
1
8
152
153
154
155
150
34
Y
5
Y
4
Y
3
Y
2
Y
1
35
36
37
271
Y
2
3
6
Y
2
3
7
Y
2
3
8
Y
2
3
9
Y
2
4
0
270 269 268
272
D
U
M
M
Y
D
U
M
M
Y
V
0
L
V
0
L
V
1
2
L
V
4
3
L
V
5
L
V
S
S
V
D
D
S
/
C
E
I
O
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
L
P
E
I
O
1
F
R
M
D
N
C
V
S
S
X
C
K
L
/
R
D
U
M
M
Y
N
C
V
5
R
V
1
2
R
V
0
R
V
0
R
V
4
3
R
D
U
M
M
Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D
I
S
P
O
F
F
NT7704
2
Pad Configuration
NT7704
1
x
ALK_L
x
x
ALK_R
x
x
Dummy Pad
x
208
209
224
225
432
433
448
x
Block Diagram
240 Bits 4 Level Driver
240 Bits Level Shifter
240 Bits Line Latch/Shift Register
Y1
Y2
Y239 Y240
V
43R
V
12R
V
0R
Level
Shifter
FR
DISPOFF
Active
Control
EIO
1
EIO
2
Control
Logic
SP Conversion & Data Control
(4 to 8 or 8 to 8)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
L/R
MD
S/C
8Bits
2
Data
Latch
Data Latch Control
/8
/240
/240
V
DD
V
SS
V
SS
/16
/16
/16
/16
/16
LP
XCK
V
5R
V
5L
V
12L
V
0L
V
43L
NT7704
3
Pad Description
Pad No.
Designation
I/O
Description
1 - 12
V
0L
P
Power supply for LCD driver
13 - 20
V
12L
P
Power supply for LCD driver
21 -28
V
43L
P
Power supply for LCD driver
29 - 40
V
5L
P
Power supply for LCD driver
41 - 66
V
SS
P
Ground (0V), these pads must be connected to each other
67 - 92
V
DD
P
Power supply for the logic system (+2.5 to +5.5V)
93 - 94
S/C
I
Segment mode/common mode selection
95 - 97
EIO
2
I/O
Input/output for chip select or data of the shift register
98, 99, 100 -
116, 117, 118
D0 - D6
I
Display data input for segment mode
119 - 121
D7
I
Display data input for Segment mode/ Dual mode data input
122 - 124
XCK
I
Display data shift clock input for segment mode
125 - 127
DISPOFF
I
Control input for deselect output level
128 - 130
LP
I
Latch pulse input/shift clock input for the shift register
131 - 133
EIO
1
I/O
Input/output for chip select or data of the shift register
134 - 136
FR
I
AC-converting signal input for LCD driver waveform
137 - 139
L/R
I
Display data shift direction selection
140 - 142
MD
I
Mode selection input
143 - 168
V
SS
P
Ground (0V), these pads must be connected to each other
169 - 180
V
5R
P
Power supply for LCD driver
181 - 188
V
43R
P
Power supply for LCD driver
189 - 196
V
12R
P
Power supply for LCD driver
197 - 208
V
0R
P
Power supply for LCD driver
209 - 448
Y1 - Y240
O
LCD driver output
NT7704
4
Input / Output Circuits
V
DD
V
SS
I
Input Signal
Applicable Pins
L/R, S/C, D0 - D6,
, LP, FR, MD
DISPOFF
Input Circuit (1)
V
DD
I
V
SS
V
SS
Input Signal
Control Signal
Applicable Pins
D7, XCK
Input Circuit (2)
NT7704
5
V
DD
I/O
V
SS
V
SS
Input Signal
Control Signal
Applicable Pins
EIO1, EIO2
Output Signal
Control Signal
V
SS
V
DD
Input / Output Circuit
Control Signal 1
Control Signal 3
Control Signal 2
Control Signal 4
V0
V12
O
V43
Applicable Pins
Y1 to Y240
V5
V
SS
LCD Driver Output circuit
NT7704
6
Pad Description
Segment mode
Symbol
Function
V
DD
Logic system power supply pin connects from +2.5 to +5.5V
V
SS
Ground pin connects to 0V
V
OR
, V
OL
V
12R
, V
12L
V
43R
, V
43L
V
5R
, V
5L
Power supply pin for LCD driver voltage bias
"
Normally, the bias voltage used is set by a resistor divider
"
Ensure that the voltages are set such that V
SS
V
5
< V
43
< V
12
< V
0
"
To further reduce the differences between the output waveforms of
the LCD driver output pins Y
1
and Y
240,
externally connect V
iR
and V
iL
(I = 0, 12, 43, 5)
D
0 -
D
7
Input pin for display data
"
In 4-bit parallel input mode, input data into the 4 pins D
0
-
D
3
. Connect D
4
- D
7
to V
SS
or V
DD
"
In 8-bit parallel input mode, input data into the 8 pins D
0
- D
XCK
Clock input pin for taking display data
"
Data is read on the falling edge of the clock pulse
LP
Latch pulse input pin for display data
"
Data is latched on the falling edge of the clock pulse
L/R
Direction selection pin for reading display data
"
When set to V
SS
level "L", data is read sequentially from Y240 to Y1
"
When set to V
DD
level "H", data is read sequentially from Y1 to Y240
DISPOFF
Control input pin for output deselect level
"
The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the
LCD driver circuit.
"
When set to V
SS
level "L", the LCD driver output pins (Y1-Y240) are set to level V
5
"
When DISPOFF is set to "L", the contents of the line latch are reset, but the display data in the data
latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled,
the driver outputs deselect level (V
12
or V
43
), then outputs the contents of the date latch onto the next
falling edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is
shown on the AC characteristics, then it can not output the reading data correctly.
FR
AC signal input for LCD driving waveform
"
The input signal is level-shifted from the logic voltage level to the driver voltage level and controls
the LCD driver circuit.
"
It normally inputs a frame inversion signal
The LCD driver output pin's output voltage level can be set to the line latch output signal and the FR signal
MD
Mode selection pin
"
When set to V
SS
level "L", 8-bit
parallel input mode is set
"
When set to V
DD
level "H",
4-bit
parallel input mode is set
NT7704
7
Segment mode continued
Symbol
Function
S/C
Segment mode/common mode selection pin
"
When set to V
DD
level "H", segment mode is set
"
When set to V
SS
level "L", common mode is set
EIO
1
, EIO
2
Input/output pin for chip selection
"
When L/R input is at V
SS
level "L", EIO
1
is set for output, and EIO
2
is set for input
"
When L/R input is at V
DD
level "H", EIO
1
is set for input, and EIO
2
is set for output
"
During output, it is set to "H" while LP* XCK is "H" and then after 240-bits of data have been read,
it is set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H"
"
During input, after the LP signal is input, the chip is selected while EI is set to "L". After 240-bits of
data have been read, the chip is deselected
Y
1
-
Y
240
LCD driver output pins
These correspond directly to each bit of the data latch, one level (V
0
, V
12
, V
43
, or
V
5
) is selected and
output
Common mode
Symbol
Function
V
DD
Logic system power supply pin connects to +2.5 to +5.5V
V
SS
Ground pin connects to 0V
V
0R
, V
0L
V
12R
, V
12L
V
43R
, V
43L
V
5R
, V
5L
Power supply pin for LCD driver voltage bias.
"
Normally, the bias voltage used is set by a resistor divider
"
Ensure the voltages are set such that V
SS
V
5
<V
43
< V
12
< V
0
To further reduce the differences between the output waveforms of the LCD driver output pins Y
1
and
Y
240,
externally connect V
iR
and V
iL
(I = 0, 12, 43, 5)
EIO
1
Bi-directional shift register shift data input/output pin
"
Is an output pin when L/R is at V
SS
level "L" and is an input pin when L/R is at V
DD
level "H"
"
When EIO
1
is used as an input pin, it will be pulled-down
"
When EIO
1
is used as an output pin, it won't be pulled-down
EIO
2
Bi-directional shift register shift data input/output pin
"
Is an input pin when L/R is at V
SS
level "L" and is an output pin when L/R is at V
DD
level "H"
"
When EIO
2
is used as an input pin, it will be pulled-down
"
When EIO
2
is used as an output pin, it won't be pulled-down
LP
Bi-directional shift register shift clock pulse input pin
"
Data is shifted on the falling edge of the clock pulse
L/R
Bi-directional shift register shift direction selection pin
"
Data is shifted from Y
240
to Y
1
when it is set to V
SS
level "L", and data is shifted from Y
1
to Y
240
when it is
set to V
DD
level "H"
NT7704
8
Common mode continued
Symbol
Function
DISPOFF
Control input pin for output deselect level
"
The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls
the LCD driver circuit
"
When set to V
SS
level "L", the LCD driver output pins (Y
1
-Y
240
) are set to level V
5
"
While set to "L", the contents of the shift resister are reset and are not reading data. When the DISPOFF
function is canceled, the driver outputs deselect level (V
12
or V
43
), and the shift data is read on the falling
edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is shown on
the AC characteristics, the shift data is not read correctly
FR
AC signal input for LCD driving waveform
"
The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the
LCD driver circuit
"
Normally, it inputs a frame inversion signal
The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR
signal
MD
Mode selection pin
"
When set to V
SS
level "L", Single Mode operation is selected. When set to V
DD
level "H", Dual Mode
operation is selected
D
7
Dual Mode data input pin
"
According to the data shift direction of the data shift register, data can be input starting from the 121st bit
When the chip is used in Dual Mode, D
7
will be pulled-down
When the chip is used in Single Mode, D
7
won't be pulled-down
S/C
Segment mode/common mode selection pin
"
When set to V
SS
level "L", common mode is set
D
0
-
D6
Not used
"
Connect D
0
-D
6
to V
SS
or V
DD
. Avoid floating
XCK
Not used
"
XCK is pull-down in common mode, so connect to V
SS
or leave open
Y
1
-
Y
240
LCD driver output pins
"
These correspond directly to each bit of the shift register, one level (V
0
, V
12,
V
43
, or V
5
) is selected and
output
NT7704
9
Functional Description
1. Block description
1.1 Active Control
In segment mode, it controls the selection or deselection of
the chip. Following a LP signal input, and after the select
signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been
completed, a select signal for cascade connection is output,
and the chip is deselected.
In common mode, it controls the input/output data of the bi-
directional pins.
1.2. SP Conversion & Data Control
In segment mode, it keeps input data which are 2 clocks of
XCK at 4-bit parallel mode into latch circuit, or keeps input
data which are 1 clock of XCK at 8-bit parallel mode into
latch circuit, after that they are put on the internal data bus 8
bits at a time.
1.3. Data Latch Control
In segment mode, it selects the state of the data latch, which
reads in the data bus signals. The shift direction is controlled
by the control logic and for every 16 bits of data read in, the
selection signal shifts one bit, based on the state of the
control circuit.
1.4. Data Latch
In segment mode, it latches the data on the data bus. The
latched state of each LCD driver output pin is controlled by
the control logic and the data latch control. 240 bits of data
are read in 20 sets of 8 bits.
1.5. Line Latch/Shift Register
In segment mode, it ensures all 240 bits which have been
read into the data latch, are simultaneously latched on to the
falling edge of the LP signal, and output to the level shift
block.
In common mode, it shifts data from the data input pin on to
the falling edge of the LP signal.
1.6. Level Shifter
It ensures the logic voltage signal is level-shifted to the LCD
driver voltage level, and output to the driver block.
1.7. 4-Level Driver
It drives the LCD driver output pins from the line latch/shift
register data, selecting one of 4 levels (V
0
, V
12
, V
43
, V
5
)
based on the S/C, FR and DISPOFF signals.
1.8. Control Logic
Controls the operation of each block. In segment mode,
when an LP signal has been input, all blocks are reset and
the control logic waits for the selection signal output from the
active control block. Once the selection signal has been
output, operation of the data latch and data transmission are
controlled, 240 bits of data are read in, and the chip is
deselected.
In common mode, it controls the direction of data shift.
NT7704
10
2. LCD Driver Output Voltage Level
The relationship between the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table
below:
2.1. Segment Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y
1
-
Y
240
)
L
L
H
V
43
L
H
H
V
5
H
L
H
V
12
H
H
H
V
0
X
X
L
V
5
Here, V
SS
V
5
< V
43
< V
12
< V
0
, H: V
DD
(+2.5 to +5.5V), L: V
SS
(0V), X: Don't care
2.2. Common Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y
1
-
Y
240
)
L
L
H
V
43
L
H
H
V
0
H
L
H
V
12
H
H
H
V
5
X
X
L
V
5
Here, V
SS
V
5
< V
43
< V
12
< V
0
, H: V
DD
(+2.5 to +5.5V), L: V
SS
(0V), X: Don't care
Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular
voltage which is assigned by specification for each power pin.
That time "Don't care" should be fixed to "H" or "L", avoiding floating.
NT7704
11
3. Relationship between the Display Data and Driver Output pins
3.1. Segment Mode:
(a) 4-bit Parallel Mode
Number of Clock
MD
L/R
EIO
1
EIO
2
Data
Input
60clock
59clock
58clcok
~
3clock
2clock
1clock
D
0
Y1
Y5
Y9
~
Y229
Y233
Y237
D
1
Y2
Y6
Y10
~
Y230
Y234
Y238
D
2
Y3
Y7
Y11
~
Y231
Y235
Y239
H
L
Output
Input
D
3
Y4
Y8
Y12
~
Y232
Y236
Y240
D
0
Y240
Y236
Y232
~
Y12
Y8
Y4
D
1
Y239
Y235
Y231
~
Y11
Y7
Y3
D
2
Y238
Y234
Y230
~
Y10
Y6
Y2
H
H
Input
Output
D
3
Y237
Y233
Y229
~
Y9
Y5
Y1
(b) 8-bit Parallel Mode
Number of Clock
MD
L/R
EIO
1
EIO
2
Data
Input
30clock
29clock
28clcok
~
3clock
2clock
1clock
D
0
Y1
Y9
Y17
~
Y217
Y225
Y233
D
1
Y2
Y10
Y18
~
Y218
Y226
Y234
D
2
Y3
Y11
Y19
~
Y219
Y227
Y235
D
3
Y4
Y12
Y20
~
Y220
Y228
Y236
D
4
Y5
Y13
Y21
~
Y221
Y229
Y237
D
5
Y6
Y14
Y22
~
Y222
Y230
Y238
D
6
Y7
Y15
Y23
~
Y223
Y231
Y239
L
L
Output
Input
D
7
Y8
Y16
Y24
~
Y224
Y232
Y240
D
0
Y240
Y232
Y224
~
Y24
Y16
Y8
D
1
Y239
Y231
Y223
~
Y23
Y15
Y7
D
2
Y238
Y230
Y222
~
Y22
Y14
Y6
D
3
Y237
Y229
Y221
~
Y21
Y13
Y5
D
4
Y236
Y228
Y220
~
Y20
Y12
Y4
D
5
Y235
Y227
Y219
~
Y19
Y11
Y3
D
6
Y234
Y226
Y218
~
Y18
Y10
Y2
L
H
Input
Output
D
7
Y233
Y225
Y217
~
Y17
Y9
Y1
NT7704
12
3.2. Common Mode
MD
L/R
Data Transfer Direction
EIO
1
EIO
2
D
7
L (shift to left)
Y240 to Y1
Output
Input
X
L
(Single)
H (shift to right)
Y1 to Y240
Input
Output
X
L (shift to left)
Y240 to Y121
Y120 to Y1
Output
Input
Input
H
(Dual)
H (shift to right)
Y1 to Y120
Y121 to Y240
Input
Output
Input
Here, L: V
SS
(0V), H: V
DD
(+2.5V to +5.5V), X: Don't care
Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
NT7704
13
4. Connection Examples of Segment Drivers
4.1. Case of L/R = "L"
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
XCK
LP
MD
D0 - D7
FR
V
SS
Y240 ---------------------->Y1
Y240 ----------------------->Y1
Y240 ---------------------->Y1
(data taking flow)
first data
last data
/8
4.2. Case of L/R = "H"
XCK
LP
MD
D0 - D7
FR
V
DD
Y1 ---------------------->Y240
(data taking flow)
first data
Y1 ---------------------->Y240
Y1 ---------------------->Y240
last data
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
XCK
LP
MD
FR
D0 - D7
L/R
EIO1
EIO2
V
SS
/8
NT7704
14
5. Timing waveform of 4-Device cascade Connection of Segment Drivers
n 1 2
n 1 2
n 1 2
n 1 2
n 1 2
device A
device B
device C
device D
First data
Last data
FR
LP
XCK
D0~D7
EI
(device A)
EO
(device A)
EO
(device B)
EO
(device C)
n: 4-bit parallel mode 60
8-bit parallel mode 30
H
L
NT7704
15
6. Connection Examples for Common Drivers
D
V
SS
(V
DD
)
V
SS
V
SS
FR
First
LP
DISPOFF
CS
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
CS
Last
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
CS
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
CS
Single Mode (Shifting towards the left)
D
V
SS
(V
DD
)
V
SS
V
DD
FR
First
LP
DISPOFF
Y240
Y1
Last
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
Single Mode (Sifting towards the right)
NT7704
16
D1
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
V
SS
(V
DD
)
V
DD
V
SS
FR
LP
DISPOFF
D2
Last2
First1
Last1 First2
Y121 Y120
Dual mode (Shifting towards the left)
D1
Y240
Y1
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
EIO1
EIO2
LP
D7
MD
L/R
FR
DISPOFF
Y240
Y1
V
SS
(V
DD
)
V
DD
V
DD
FR
LP
DISPOFF
D2
Last2
First1
Last1 First2
Y240
Y1
Y121
Y120
Dual mode (Shifting towards the right)
NT7704
17
7. Precaution
Be careful when connecting or disconnecting the power
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur if voltage is
supplied to the LCD driver power supply while the logic system power supply is floating.
The details are as follows:
!
When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore,
when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power.
!
We recommend that you connect a serial resistor (50-100
) or fuse to the LCD driver power V
0
of the system as a current
limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade.
In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore, connect the
LCD driver power supply only after resetting the logic condition of this LSI inside to the DISPOFF function. After that, the
DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the
power, set the LCD driver output pins to level V
5
on the DISPOFF function. After that, disconnect the logic system power after
disconnecting the LCD driver power.
When connecting the power supply, follow the recommended sequence shown.
V
DD
V
DD
V
SS
DISPOFF
V
0
V
DD
V
SS
V
SS
V
0
NT7704
18
Absolute Maximum Rating*
DC Supply Voltage V
DD
. . . . . . . . . . . . . -0.3V to +7.0V
DC Supply Voltage V
0
. . . . . . . . . . . . . . -0.3V to +30V
Input Voltage . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Operating Ambient Temperature . . . . -30
C to +85
C
Storage Temperature . . . . . . . . . . . . .-45
C to +125
C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device under these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
Electrical Characteristics
DC Characteristics
Segment Mode (V
SS
= V
5
= 0V, V
DD
= 2.5 - 5.5V, V
0
= 15 to 30 V, and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Operating Voltage 1
V
DD
2.5
-
5.5
V
Operating Voltage 2
V
0
15
-
30
V
Input high voltage
V
IH
0.8 V
DD
-
-
V
Input low voltage
V
IL
-
-
0.2 V
DD
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO
1
,
EIO
2
, DISPOFF pins
Output high voltage
V
OH
V
DD
- 0.4
-
-
V
EIO
1
, EIO
2
pins, I
OH
= -0.4mA
Output low voltage
V
OL
-
-
+0.4
V
EIO
1
, EIO
2
pins, I
OL
= +0.4mA
Input leakage current 1
I
IH
-
-
+1.0
A
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO
1
,
EIO
2
, DISPOFF pins, V
I
= V
DD
Input leakage current 2
I
IL
-
-
-1.0
A
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO
1
,
EIO
2
, DISPOFF pins, V
I
= V
SS
-
1.5
2.0
V0 = +30.0V
Output resistance
R
ON
-
2.0
2.5
k
V0 = +20.0V
Y
1 -
Y
240
pins,
N
O
V
= 0.5V
Stand-by current
I
SB
-
-
10
A
V
SS
pin, Note 1
Consumed current (1)
(Deselection)
I
DD1
-
-
2
mA
V
DD
pin, Note 2
Consumed current (2)
(Selection)
I
DD2
-
-
12
mA
V
DD
pin, Note 3
Consumed current
I
0
-
-
1.5
mA
V
0
pin, Note 4
Note:
1. V
DD
= +5.0V, V
0
= +30V, V
I
= V
SS
2. V
DD
= +5.0V, V
0
= +30V, f
XCK
= 20MHz, No-load, EI = V
DD
The input data is turned over by the data taking clock (4-bit Parallel input mode)
3. V
DD
= +5.0V, V
0
= +30V, f
XCK
= 20MHz, No-load. EI = V
SS
The input data is turned over by the data taking clock (4-bit parallel input mode)
4. V
DD
= +5.0V, V
0
= +30V, f
XCK
= 20MHz, f
LP
= 41.6kHz. f
FR
= 80 Hz, No-load
The input data is turned over by the data taking clock (4-bit parallel-input mode)
NT7704
19
Common Mode (V
SS
= V
5
= 0V, V
DD
= 2.5 - 5.5V, V
0
= 15 to 30 V, and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Operating Voltage
V
DD
2.5
-
5.5
V
Operating Voltage
V
0
15
-
30
V
Input high voltage
V
IH
0.8 V
DD
-
-
V
Input low voltage
V
IL
-
-
0.2 V
DD
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO
1
,
EIO
2
, DISPOFF pins
Output high voltage
V
OH
V
DD
- 0.4
-
-
V
EIO
1
, EIO
2
pins, I
OH
= -0.4mA
Output low voltage
V
OL
-
-
+0.4
V
EIO
1
, EIO
2
pins, I
OL
= +0.4mA
Input leakage current 1
I
IH
-
-
+1.0
A
D0 - 6, LP, L/R, FR, MD, S/C and
DISPOFF pins, V
I
= V
DD
Input leakage current 2
I
IL
-
-
-1.0
A
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins, V
I
= V
SS
Input pull down current
I
PD
-
-
100
A
XCK, EIO
1
, EIO
2
, D7 pins
-
1.5
2.0
V0 = +30.0V
Output resistance
R
ON
-
2.0
2.5
k
V0 = +20.0V
Y
1 -
Y
240
pins,
N
O
V
= 0.5V
Stand-by current
I
SB
-
-
10
A
V
SS
pin, Note 1
Consumed current (1)
I
DD
-
-
120
A
V
DD
pin, Note 2
Consumed current (2)
I
0
-
-
240
A
V
0
pin, Note 2
Note:
1. V
DD
= +5.0V, V
0
= +30.0V, V
I
= V
SS
2. V
DD
= +5.0V, V
0
= +30.0V, f
LP
= 41.6KHz, f
FR
= 80Hz, case of 1/480 duty operation, No-load
NT7704
20
AC Characteristics
Segment Mode 1 (V
SS
= V
5
= 0V, V
DD
= 4.5 - 5.5V, V
0
= 15 to 30V, and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
t
WCK
50
-
ns
tr, tf
10ns, Note 1
Shift clock "H" pulse width
t
WCKH
15
-
ns
Shift clock "L" pulse width
t
WCKL
15
-
ns
Data setup time
t
DS
10
-
ns
Data hole time
t
DH
12
-
ns
Latch pulse "H" pulse width
t
WLPH
15
-
ns
Shift clock rise to Latch pulse rise time
t
LD
0
-
ns
Shift clock fall to Latch pulse fall time
t
SL
30
-
ns
Latch pulse rise to Shift clock rise time
t
LS
25
-
ns
Latch pulse fall to Shift clock rise time
t
LH
25
-
ns
Input signal rise time
t
r
-
50
ns
Note 2
Input signal fall time
t
f
-
50
ns
Note 2
Enable setup time
t
S
10
-
ns
DISPOFF Removal time
t
SD
100
-
ns
DISPOFF enable pulse width
t
WDL
1.2
-
s
Output delay time (1)
t
D
-
30
ns
CL = 15pF
Output delay time (2)
t
pd1
, t
pd2
-
1.2
s
CL = 15pF
Output delay time (3)
t
pd3
-
1.2
s
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (t
CK
-t
WCKII
-t
wckl
)/2 is the maximum in the case of high speed operation.
NT7704
21
Segment Mode 2 (V
SS
= V
5
= 0V, V
DD
= 3.0 - 4.5V, V
0
= 15 to 30V, and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
t
WCK
66
-
ns
tr, tf
10ns, Note 1
Shift clock "H" pulse width
t
WCKH
23
-
ns
Shift clock "L" pulse width
t
WCKL
23
-
ns
Data setup time
t
DS
15
-
ns
Data hole time
t
DH
23
-
ns
Latch pulse "H" pulse width
t
WLPH
30
-
ns
Shift clock rise to Latch pulse rise time
t
LD
0
-
ns
Shift clock fall to Latch pulse fall time
t
SL
50
-
ns
Latch pulse rise to Shift clock rise time
t
LS
30
-
ns
Latch pulse fall to Shift clock fall time
t
LH
30
-
ns
Input signal rise time
t
r
-
50
ns
Note 2
Input signal fall time
t
f
-
50
ns
Note 2
Enable setup time
t
S
15
-
ns
DISPOFF Removal time
t
SD
100
-
ns
DISPOFF
enable pulse width
t
WDL
1.2
-
s
Output delay time (1)
t
D
-
41
ns
CL = 15pF
Output delay time (2)
t
pd1
, t
pd2
-
1.2
s
CL = 15pF
Output delay time (3)
t
pd3
-
1.2
s
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (t
CK
-t
WCKII
-t
WCKL
)/2 is the maximum in the case of high speed operation.
NT7704
22
Segment Mode 3 (V
SS
= V
5
= 0V, V
DD
= 2.5 - 3.0V, V
0
= 15 to 30V, and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
t
WCK
82
-
ns
tr, tf
10ns, Note 1
Shift clock "H" pulse width
t
WCKH
28
-
ns
Shift clock "L" pulse width
t
WCKL
28
-
ns
Data setup time
t
DS
20
-
ns
Data hole time
t
DH
23
-
ns
Latch pulse "H" pulse width
t
WLPH
30
-
ns
Shift clock rise to Latch pulse rise time
t
LD
0
-
ns
Shift clock fall to Latch pulse fall time
t
SL
65
-
ns
Latch pulse rise to Shift clock rise time
t
LS
30
-
ns
Latch pulse fall to Shift clock fall time
t
LH
30
-
ns
Input signal rise time
t
r
-
50
ns
Note 2
Input signal fall time
t
f
-
50
ns
Note 2
Enable setup time
t
S
15
-
ns
DISPOFF Removal time
t
SD
100
-
ns
DISPOFF
enable pulse width
t
WDL
1.2
-
s
Output delay time (1)
t
D
-
57
ns
CL = 15pF
Output delay time (2)
t
pd1
, t
pd2
-
1.2
s
CL = 15pF
Output delay time (3)
t
pd3
-
1.2
s
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (t
CK
-t
WCKII
-t
WCKL
)/2 is the maximum in the case of high speed operation.
NT7704
23
Timing waveform of the Segment Mode
tSL
LP
LAST DATA
TOP DATA
tLD
tLS
tWCKL
tr
tr
tWCK
tDS
tDH
XCK
D0 - D7
DISPOFF
tLH
tWDL
tSD
tWLPH
tWCKH
tpd1
tpd2
tpd3
FR
LP
Y1 - Y240
DISPOFF
XCK
EO
tS
1
2
tD
n: 4-bit parallel mode 60
8-bit parallel mode 30
LP
EI
n
NT7704
24
Common Mode (V
SS
= V
5
= 0V, V
DD
= 2.5 - 5.5V, V
0
= 15 to 30V and T
A
= -30 to +85
C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
t
WLP
250
-
-
ns
t
r
, t
f
20ns
15
-
-
ns
V
DD
= +5.0V
10%
Shift clock "H" pulse width
t
WLPH
30
-
-
ns
V
DD
= +2.5 - +4.5V
Data setup time
t
SU
30
-
-
ns
Data hole time
t
H
50
-
-
ns
Input signal rise time
t
r
-
50
ns
Input signal fall time
t
f
-
50
ns
DISPOFF Removal time
t
SD
100
-
-
ns
DISPOFF enable pulse width
t
WDL
1.2
-
-
s
Output delay time (1)
t
DL
-
-
200
ns
C
L
= 15pF
Output delay time (2)
t
pd1
, t
pd2
-
-
1.2
s
C
L
= 15pF
Output delay time (3)
t
pd3
-
-
1.2
s
C
L
= 15pF
NT7704
25
Timing Characteristics of Common Mode
tr
tf
LP
DISPOFF
tWDL
tSD
tWLP
tWLPH
tSU
tH
tDL
EIO2
(DI7)
EIO1
tpd1
tpd2
tpd3
FR
LP
Y1 - Y240
DISPOFF
NT7704
26
Application Circuit (for reference only)
YD
C
O
M
1
C
O
M
2
C
O
M
3
C
O
M
4
7
9
C
O
M
4
8
0
SEG1
SEG2
SEG3
SEG960
SEG959
LCD controller
/8
FR
LP
XCK
EIO1
MD
S/C
L/R
D0 - D7
EIO2
FR
LP
XCK
EIO1
MD
S/C
L/R
D0 - D7
EIO2
FR
LP
XCK
EIO1
MD
S/C
L/R
D0 - D7
EIO2
FR
LP
XCK
EIO1
MD
S/C
L/R
D0 - D7
EIO2
/8
Y1 - Y240
Y1 - Y240
Y1 - Y240
Y1 - Y240
/5
/5
FR
LP
XCK
XD
0
- XD
7
DISPOFF
V
SS
(case of 1/n bias)
NT7704*4
NT7704*2
960*480 DOT MATRIX
LCD PANEL
DISPOFF
DISPOFF
DISPOFF
DISPOFF
V
DD
V
5
V
1
V
2
V
3
4
V
(n-4)R
R
R
R
R
V
0
V
0
V
SS
Note: V
0
-V
1
>1.5V
FR
LP
XCK
EIO1
MD
S/C
L/R
D0 - D7
EIO2
DISPOFF
Y1 - Y240
FR
LP
XCK
EIO1
MD
S/C
L/R
EIO2
DISPOFF
Y1 - Y240
D0 - D7
NT7704
27
Bonding Diagram
NT7704
12968um
1168um
1
x
ALK_L
x
x
ALK_R
x
x
Dummy Pad
x
208
209
224
225
432
433
448
( 0 , 0 )
X
Y
x
Pad Location
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
1
V
0L
-6220
-521
31
V
5L
-4410
-521
2
V
0L
-6150
-521
32
V
5L
-4350
-521
3
V
0L
-6090
-521
33
V
5L
-4290
-521
4
V
0L
-6030
-521
34
V
5L
-4230
-521
5
V
0L
-5970
-521
35
V
5L
-4170
-521
6
V
0L
-5910
-521
36
V
5L
-4110
-521
7
V
0L
-5850
-521
37
V
5L
-4050
-521
8
V
0L
-5790
-521
38
V
5L
-3990
-521
9
V
0L
-5730
-521
39
V
5L
-3930
-521
10
V
0L
-5670
-521
40
V
5L
-3870
-521
11
V
0L
-5610
-521
41
V
SS
-3810
-521
12
V
0L
-5550
-521
42
V
SS
-3750
-521
13
V
12L
-5490
-521
43
V
SS
-3690
-521
14
V
12L
-5430
-521
44
V
SS
-3630
-521
15
V
12L
-5370
-521
45
V
SS
-3570
-521
16
V
12L
-5310
-521
46
V
SS
-3510
-521
17
V
12L
-5250
-521
47
V
SS
-3450
-521
18
V
12L
-5190
-521
48
V
SS
-3390
-521
19
V
12L
-5130
-521
49
V
SS
-3330
-521
20
V
12L
-5070
-521
50
V
SS
-3270
-521
21
V
43L
-5010
-521
51
V
SS
-3210
-521
22
V
43L
-4950
-521
52
V
SS
-3150
-521
23
V
43L
-4890
-521
53
V
SS
-3090
-521
24
V
43L
-4830
-521
54
V
SS
-3030
-521
25
V
43L
-4770
-521
55
V
SS
-2970
-521
26
V
43L
-4710
-521
56
V
SS
-2910
-521
27
V
43L
-4650
-521
57
V
SS
-2850
-521
28
V
43L
-4590
-521
58
V
SS
-2790
-521
29
V
5L
-4530
-521
59
V
SS
-2730
-521
30
V
5L
-4470
-521
60
V
SS
-2670
-521
NT7704
28
Pad Location
(continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
61
V
SS
-2610
-521
101
D1
-210
-521
62
V
SS
-2550
-521
102
D1
-150
-521
63
V
SS
-2490
-521
103
D1
-90
-521
64
V
SS
-2430
-521
104
D2
-30
-521
65
V
SS
-2370
-521
105
D2
30
-521
66
V
SS
-2310
-521
106
D2
90
-521
67
V
DD
-2250
-521
107
D3
150
-521
68
V
DD
-2190
-521
108
D3
210
-521
69
V
DD
-2130
-521
109
D3
270
-521
70
V
DD
-2070
-521
110
D4
330
-521
71
V
DD
-2010
-521
111
D4
390
-521
72
V
DD
-1950
-521
112
D4
450
-521
73
V
DD
-1890
-521
113
D5
510
-521
74
V
DD
-1830
-521
114
D5
570
-521
75
V
DD
-1770
-521
115
D5
630
-521
76
V
DD
-1710
-521
116
D6
690
-521
77
V
DD
-1650
-521
117
D6
750
-521
78
V
DD
-1590
-521
118
D6
810
-521
79
V
DD
-1530
-521
119
D7
870
-521
80
V
DD
-1470
-521
120
D7
930
-521
81
V
DD
-1410
-521
121
D7
990
-521
82
V
DD
-1350
-521
122
XCK
1050
-521
83
V
DD
-1290
-521
123
XCK
1110
-521
84
V
DD
-1230
-521
124
XCK
1170
-521
85
V
DD
-1170
-521
125
DISPOFF
1230
-521
86
V
DD
-1110
-521
126
DISPOFF
1290
-521
87
V
DD
-1050
-521
127
DISPOFF
1350
-521
88
V
DD
-990
-521
128
LP
1410
-521
89
V
DD
-930
-521
129
LP
1470
-521
90
V
DD
-870
-521
130
LP
1530
-521
91
V
DD
-810
-521
131
EIO
1
1590
-521
92
V
DD
-750
-521
132
EIO
1
1650
-521
93
S/C
-690
-521
133
EIO
1
1710
-521
94
S/C
-630
-521
134
FR
1770
-521
95
EIO
2
-570
-521
135
FR
1830
-521
96
EIO
2
-510
-521
136
FR
1890
-521
97
EIO
2
-450
-521
137
L/R
1950
-521
98
D0
-390
-521
139
L/R
2010
-521
99
D0
-330
-521
139
L/R
2070
-521
100
D0
-270
-521
140
MD
2130
-521
NT7704
29
Pad Location
(continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
141
MD
2190
-521
181
V
43R
4590
-521
142
MD
2250
-521
182
V
43R
4650
-521
143
V
SS
2310
-521
183
V
43R
4710
-521
144
V
SS
2370
-521
184
V
43R
4770
-521
145
V
SS
2430
-521
185
V
43R
4830
-521
146
V
SS
2490
-521
186
V
43R
4890
-521
147
V
SS
2550
-521
187
V
43R
4950
-521
148
V
SS
2610
-521
188
V
43R
5010
-521
149
V
SS
2670
-521
189
V
12R
5070
-521
150
V
SS
2730
-521
190
V
12R
5130
-521
151
V
SS
2790
-521
191
V
12R
5190
-521
152
V
SS
2850
-521
192
V
12R
5250
-521
153
V
SS
2910
-521
193
V
12R
5310
-521
154
V
SS
2970
-521
194
V
12R
5370
-521
155
V
SS
3030
-521
195
V
12R
5430
-521
156
V
SS
3090
-521
196
V
12R
5490
-521
157
V
SS
3150
-521
197
V
0R
5550
-521
158
V
SS
3210
-521
198
V
0R
5610
-521
159
V
SS
3270
-521
199
V
0R
5670
-521
160
V
SS
3330
-521
200
V
0R
5730
-521
161
V
SS
3390
-521
201
V
0R
5790
-521
162
V
SS
3450
-521
202
V
0R
5850
-521
163
V
SS
3510
-521
203
V
0R
5910
-521
164
V
SS
3570
-521
204
V
0R
5970
-521
165
V
SS
3630
-521
205
V
0R
6030
-521
166
V
SS
3690
-521
206
V
0R
6090
-521
167
V
SS
3750
-521
207
V
0R
6150
-521
168
V
SS
3810
-521
208
V
0R
6220
-521
169
V
5R
3870
-521
209
Y1
6430
-450
170
V
5R
3930
-521
210
Y2
6430
-390
171
V
5R
3990
-521
211
Y3
6430
-330
172
V
5R
4050
-521
212
Y4
6430
-270
173
V
5R
4110
-521
213
Y5
6430
-210
174
V
5R
4170
-521
214
Y6
6430
-150
175
V
5R
4230
-521
215
Y7
6430
-90
176
V
5R
4290
-521
216
Y8
6430
-30
177
V
5R
4350
-521
217
Y9
6430
30
178
V
5R
4410
-521
218
Y10
6430
90
179
V
5R
4470
-521
219
Y11
6430
150
180
V
5R
4530
-521
220
Y12
6430
210
NT7704
30
Pad Location
(continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
221
Y13
6430
270
261
Y53
4050
529
222
Y14
6430
330
262
Y54
3990
529
223
Y15
6430
390
263
Y55
3930
529
224
Y16
6430
450
264
Y56
3870
529
225
Y17
6210
529
265
Y57
3810
529
226
Y18
6150
529
266
Y58
3750
529
227
Y19
6090
529
267
Y59
3690
529
228
Y20
6030
529
268
Y60
3630
529
229
Y21
5970
529
269
Y61
3570
529
230
Y22
5910
529
270
Y62
3510
529
231
Y23
5850
529
271
Y63
3450
529
232
Y24
5790
529
272
Y64
3390
529
233
Y25
5730
529
273
Y65
3330
529
234
Y26
5670
529
274
Y66
3270
529
235
Y27
5610
529
275
Y67
3210
529
236
Y28
5550
529
276
Y68
3150
529
237
Y29
5490
529
277
Y69
3090
529
238
Y30
5430
529
278
Y70
3030
529
239
Y31
5370
529
279
Y71
2970
529
240
Y32
5310
529
280
Y72
2910
529
241
Y33
5250
529
281
Y73
2850
529
242
Y34
5190
529
282
Y74
2790
529
243
Y35
5130
529
283
Y75
2730
529
244
Y36
5070
529
284
Y76
2670
529
245
Y37
5010
529
285
Y77
2610
529
246
Y38
4950
529
286
Y78
2550
529
247
Y39
4890
529
287
Y79
2490
529
248
Y40
4830
529
288
Y80
2430
529
249
Y41
4770
529
289
Y81
2370
529
250
Y42
4710
529
290
Y82
2310
529
251
Y43
4650
529
291
Y83
2250
529
252
Y44
4590
529
292
Y84
2190
529
253
Y45
4530
529
293
Y85
2130
529
254
Y46
4470
529
294
Y86
2070
529
255
Y47
4410
529
295
Y87
2010
529
256
Y48
4350
529
296
Y88
1950
529
257
Y49
4290
529
297
Y89
1890
529
258
Y50
4230
529
298
Y90
1830
529
259
Y51
4170
529
299
Y91
1770
529
260
Y52
4110
529
300
Y92
1710
529
NT7704
31
Pad Location
(continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
301
Y93
1650
529
341
Y133
-750
529
302
Y94
1590
529
342
Y134
-810
529
303
Y95
1530
529
343
Y135
-870
529
304
Y96
1470
529
344
Y136
-930
529
305
Y97
1410
529
345
Y137
-990
529
306
Y98
1350
529
346
Y138
-1050
529
307
Y99
1290
529
347
Y139
-1110
529
308
Y100
1230
529
348
Y140
-1170
529
309
Y101
1170
529
349
Y141
-1230
529
310
Y102
1110
529
350
Y142
-1290
529
311
Y103
1050
529
351
Y143
-1350
529
312
Y104
990
529
352
Y144
-1410
529
313
Y105
930
529
353
Y145
-1470
529
314
Y106
870
529
354
Y146
-1530
529
315
Y107
810
529
355
Y147
-1590
529
316
Y108
750
529
356
Y148
-1650
529
317
Y109
690
529
357
Y149
-1710
529
318
Y110
630
529
358
Y150
-1770
529
319
Y111
570
529
359
Y151
-1830
529
320
Y112
510
529
360
Y152
-1890
529
321
Y113
450
529
361
Y153
-1950
529
322
Y114
390
529
362
Y154
-2010
529
323
Y115
330
529
363
Y155
-2070
529
324
Y116
270
529
364
Y156
-2130
529
325
Y117
210
529
365
Y157
-2190
529
326
Y118
150
529
366
Y158
-2250
529
327
Y119
90
529
367
Y159
-2310
529
328
Y120
30
529
368
Y160
-2370
529
329
Y121
-30
529
369
Y161
-2430
529
330
Y122
-90
529
370
Y162
-2490
529
331
Y123
-150
529
371
Y163
-2550
529
332
Y124
-210
529
372
Y164
-2610
529
333
Y125
-270
529
373
Y165
-2670
529
334
Y126
-330
529
374
Y166
-2730
529
335
Y127
-390
529
375
Y167
-2790
529
336
Y128
-450
529
376
Y168
-2850
529
337
Y129
-510
529
377
Y169
-2910
529
338
Y130
-570
529
378
Y170
-2970
529
339
Y131
-630
529
379
Y171
-3030
529
340
Y132
-690
529
380
Y172
-3090
529
NT7704
32
Pad Location
(continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
381
Y173
-3150
529
416
Y208
-5250
529
382
Y174
-3210
529
417
Y209
-5310
529
383
Y175
-3270
529
418
Y210
-5370
529
384
Y176
-3330
529
419
Y211
-5430
529
385
Y177
-3390
529
420
Y212
-5490
529
386
Y178
-3450
529
421
Y213
-5550
529
387
Y179
-3510
529
422
Y214
-5610
529
388
Y180
-3570
529
423
Y215
-5670
529
389
Y181
-3630
529
424
Y216
-5730
529
390
Y182
-3690
529
425
Y217
-5790
529
391
Y183
-3750
529
426
Y218
-5850
529
392
Y184
-3810
529
427
Y219
-5910
529
393
Y185
-3870
529
428
Y220
-5970
529
394
Y186
-3930
529
429
Y221
-6030
529
395
Y187
-3990
529
430
Y222
-6090
529
396
Y188
-4050
529
431
Y223
-6150
529
397
Y189
-4110
529
432
Y224
-6210
529
398
Y190
-4170
529
433
Y225
-6430
450
399
Y191
-4230
529
434
Y226
-6430
390
400
Y192
-4290
529
435
Y227
-6430
330
401
Y193
-4350
529
436
Y228
-6430
270
402
Y194
-4410
529
437
Y229
-6430
210
403
Y195
-4470
529
438
Y230
-6430
150
404
Y196
-4530
529
439
Y231
-6430
90
405
Y197
-4590
529
440
Y232
-6430
30
406
Y198
-4650
529
441
Y233
-6430
-30
407
Y199
-4710
529
442
Y234
-6430
-90
408
Y200
-4770
529
443
Y235
-6430
-150
409
Y201
-4830
529
444
Y236
-6430
-210
410
Y202
-4890
529
445
Y237
-6430
-270
411
Y203
-4950
529
446
Y238
-6430
-330
412
Y204
-5010
529
447
Y239
-6430
-390
413
Y205
-5070
529
448
Y240
-6430
-450
414
Y206
-5130
529
ALK_L
-6318
-533
415
Y207
-5190
529
ALK_R
6318
-533
NT7704
33
Dummy Pad Location (Total: 6 pin)
NO.
X
Y
NO.
X
Y
1
6430
-520
4
-6280
529
2
6430
520
5
-6430
520
3
6280
529
6
-6430
-520
NT7704
34
Package Information
A1
A2
D1
D2
n1
m1
A1
A2
D1
C2
208
m1
n1
D2
C1
D1
C1
D1
n1
m1
16
n1
m1
H
D2
C1
D1
C1
D1
n1
m1
16
n1
m1
H
NT7704
B
J
D1
r
r
m2
n1
m2
4
n1
m2
m2
n1
2
m2
n1
m2
C3
m1
n2
76
m3
n2
m2
C3
D2
m1
n2
B
J
D1
D2
m3
m3
65
m1
n2 (L)
65
m1
n2 (R)
Chip Outline Dimensions
unit: um
Symbol
Dimensions in um
Symbol
Dimensions in um
A1
204
H
51
A2
54
J
166
B
264
m1
39
C1
64
m2
55
C2
55
m3
38
C3
63
n1
72
D1
70
n2
90
D2
60
r
35
NT7704
35
TCP Pin Layout
NT7704
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DUMMY
V0L
V0L
V12L
V43L
V5L
VSS
VDD
S/C
EIO2
D0
D1
D2
D3
D4
D5
D6
D7
LP
EIO1
FR
L/R
MD
NC
VSS
NC
V5R
V43R
DISPOFF
XCK
31
32
V12R
V0R
V0R
DUMMY
33
34
35
36
37
DUMMY
Y1
Y2
Y4
Y3
Y5
268
269
270
271
272
Y236
Y237
Y238
Y239
Y240
DUMMY
151
152
153
154
150
155
Y118
Y119
Y120
Y122
Y121
Y123
(COPPER SIDE VIEW)
NT7704
36
External View of TCP Pins
N
T
7704H
- T
ABF
4
NT7704
37
Cautions concerning storage:
1. When storing the product, it is recommended that it be left in its shipping package.
After the seal of the packing bag has been broke, store the products in a nitrogen atmosphere.
2. Storage conditions :
Storage state
Storage conditions
unopened (less than 90 days)
Temperature: 5 to 30
; humidity: 80%RH or less
After seal of broken (less than 30 days)
Room temperature, dry nitrogen atmosphere
3. Don't store in a location exposed to corrosive gas or excessive dust.
4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature.
5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking.
6. Deterioration of the plating may occur after long-term storage, so special care is required.
It is recommended that the products be inspected before use.
NT7704
38
Tray Information
a
e
f
W2
W1
T1
T2
SECTION X-X
b
YY
4
25=100
h
g
e
f
T1
T2
W2
SECTION Y-Y
d
c
h
g
W1
X
X
H30-523
59-25
Tray Outline Dimensions
unit: mm
Symbol
Dimensions in mm
Symbol
Dimensions in mm
a
1.30
g
0.64
b
2.67
h
4.20
c
13.30
W1
76.0
d
16.26
W2
68.0
e
1.60
T1
71.0
f
1.40
T2
68.3
NT7704
39
Ordering Information
Part No.
Package
NT7704H-BDT
Au bump on chip tray
NT7704H-TABF4
TCP Form
NT7704
40
Product Spec. Change Notice
NT7704 Specification Revision History
Version
Content
Date
1.0
TCP and tray information addition (Page 36-39)
Dec. 2001
0.2
Gold Bump Size revision (Page 34)
m1: 45
39, m2: 58
55
Sep. 2001
0.1
Pad Location Addition
Nov. 2000
0.0
Original
Nov. 2000
PDF 
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