preliminary
CF5072 series
NIPPON PRECISION CIRCUITS INC.--1
155MHz VCXO Module ICs
OVERVIEW
The CF5072 series are 155MHz VCXO ICs. They incorporate a 155.52MHz fundamental frequency oscillator
circuit and a differential LVPECL output circuit on a single chip. The oscillator circuit features characteristics
optimized for VCXO operation, and includes a varicap connection pin. The CF5072 series can be configured
with few external components, making them ideal as miniature VCXO modules.
FEATURES
I
3.0 to 3.6V operating supply voltage range
I
80MHz to 200MHz oscillator frequency range
I
Differential LVPECL output
I
50 5% output duty
(measured at the output crossing point)
I
Output enable function
High impedance output when OE = LOW
(oscillator continues running)
I
-
40 to 85
C operating temperature range
I
Chip form (CF5072
)
BLOCK DIAGRAM
ORDERING INFORMATION
ESD sensitive device:
The XR pin is not equipped with a protection circuit. Accordingly, its electrostatic withstand voltage is significantly lower
than that of the other pins.
ESD breakdown prevention handling precautions are strongly recommended.
XC
XIN
XR
VC
L
S
R
P
HVC350B
R
VC
R
S
C2
C1
100pF
Differential
Converter
X'tal
VSS1
Pre-buffer
ECL
VDD2
Oscillator block equivlent circuit
VSS2
OE
OUT
OUTN
VDD1
Device
Package
CF5072
-
1
Chip form
preliminary
CF5072 series
NIPPON PRECISION CIRCUITS INC.--2
FUNCTIONAL DESCRIPTION
Oscillator Equivalent Circuit
The oscillator can be represented by the equivalent circuit shown below. The crystal unit is connected to XIN,
and the other terminal is connected to the L
S
and R
P
network. A varicap is added with cathode connected to
XR, and anode connected to XC.
The control voltage is applied to the VC pin, with high-resistance element connected between VC and XR
built-in.
Oscillator internal capacitors
Recommended external constants
Output Circuit
The output is enabled/disabled using the OE pin. Outputs are high impedance when disabled. The OE pin logic
is shown in the following table.
XC
XIN
VSS1
XR
VC
L
S
R
P
HVC350B
R
VC
R
S
C2
C1
100pF
To differential
converter
VC input
X'tal
Version
Internal capacitance [pF] (design value)
C1
C2
CF5072AA
11.2
14.4
Oscillator
frequency
L
S
[nH]
R
P
[k
]
1
1. R
P
is a damping resistor to prevent parasitic oscillation due the
combined effects of the external inductor (expander coil) and varicap
capacitance/internal capacitance. It is recommended that R
P
be
connected in parallel with L
S
.
155.52MHz
220
2.2
180
1.8
OE
OUT
OUTN
HIGH or open
CLK output
CLK output
LOW
High impedance
High impedance
OUT
OE = HIGH: OFF
OE = LOW: ON
VDD1
OUTN
OE = HIGH: ON
OE = LOW: OFF
From pre-buffer
preliminary
CF5072 series
NIPPON PRECISION CIRCUITS INC.--3
PAD LAYOUT
(Unit: m)
PAD DESCRIPTION AND DIMENSIONS
Chip size: 1.82
1.00mm
Chip thickness: 300 30m
Pad size: 110
100m (TEST pin only = 90
90m)
Chip base: V
SS
potential
Pad No.
Name
I/O
Function
Pad dimensions [m]
Pad size [m]
X
Y
X
Y
1
VSS1
Oscillator ground
125
135
110
100
2
TEST
I
IC test pin (leave open circuit for normal operation)
1283
160
90
90
3
OE
I
Output enable, with pull-up resistor built-in
1695
135
110
100
4
VSS2
Ground
1695
268
110
100
5
OUT
O
Differential PECL non-inverting output (true)
1695
460
110
100
6
OUTN
O
Differential PECL inverting output (complementary)
1695
673
110
100
7
VDD1
ECL buffer supply
1695
865
110
100
8
VDD2
Supply
643
865
100
110
9
XIN
I
Crystal unit connection
125
828
110
100
10
XC
I
Varicap anode connection
125
708
110
100
11
NC
No connection
125
495
110
100
12
XR
1
1. The XR pin electrostatic withstand voltage is weaker than the other pins. The electrostatic withstand voltage of pins, excluding XR, is the same as that
for existing NPC devices.
I
Varicap cathode connection and inductor connection
125
375
110
100
13
VC
I
Control voltage pin
125
255
110
100
(1820,1000)
XIN
1
13
12
11
10
9
6
7
8
3
4
5
2
DA5072
XC
NC
XR
VC
VSS1
VDD2
TEST
VDD1
OUTN
OUT
VSS2
OE
(0,0)
X
Y
preliminary
CF5072 series
NIPPON PRECISION CIRCUITS INC.--4
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
DC Characteristics
Recommended operating conditions apply unless otherwise noted
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage range
V
DD
V
SS
-
0.5 to V
SS
+ 7.0
V
Input voltage range
V
IN
V
SS
-
0.5 to V
DD
+ 0.5
V
Storage temperature range
T
STG
-
65 to 150
C
Parameter
Symbol
Conditions
Rating
Unit
Min
Typ
Max
Supply voltage
V
DD
3.0
3.6
V
Operating temperature
T
OPR
-
40
85
C
Output load
R
L
Terminated to V
DD
-
2V
50
Output frequency
f
OUT
80
200
MHz
Parameter
Symbol
Conditions
Rating
Unit
Min
Typ
Max
Current consumption
I
DD
Measurement circuit 1, output terminated
to V
DD
-
2V, OE = OPEN
50
88
mA
OUT/OUTN HIGH-level output voltage
V
OH
Measurement circuit 2,
V
DD
= 3.3V, OE = OPEN
Ta = 0 to 85
C
2.275
2.350
2.420
V
Ta =
-
40
C
2.215
2.295
2.420
V
OUT/OUTN LOW-level output voltage
V
OL
Ta = 0 to 85
C
1.490
1.600
1.680
V
Ta =
-
40
C
1.470
1.605
1.745
V
OE HIGH-level input voltage
V
IH
Measurement circuit 3
0.7V
CC
V
OE LOW-level input voltage
V
IL
Measurement circuit 3
0.3V
CC
V
OE LOW-level input current
I
IL
Measurement circuit 4, V
IL
= 0V
-
20
A
Input impedance
Z
IN
Measurement circuit 5, measured between
supply and VC
10
M
VC resistance
R
VC
Measurement circuit 6, measured between
VC and XR
100
150
200
k
Pull-down resistance
R
S
Measurement circuit 7, measured between
VSS and XC
10
20
40
k
preliminary
CF5072 series
NIPPON PRECISION CIRCUITS INC.--5
AC Characteristics
Recommended operating conditions apply unless otherwise noted
Parameter
Symbol
Conditions
Rating
Unit
Min
Typ
Max
Output duty cycle 1
Duty1
Measurement circuit 1, measured at output
crossing point, Ta = 25
C, V
DD
= 3.3V
45
50
55
%
Output duty cycle 2
Duty2
Measurement circuit 1, measured at 50% output
swing, Ta = 25
C, V
DD
= 3.3V
45
50
55
%
Output swing
1
1. The said values are measured by using the NPC standard jig.
V
Opp
Measurement circuit 1, peak-to-peak of output
waveform
0.4
V
Output rise time
t
r
Measurement circuit 1, output swing 20% to 80%
0.5
1
ns
Output fall time
t
f
Measurement circuit 1, output swing 80% to 20%
0.5
1
ns
Output enable delay time
t
OE
Measurement circuit 3, Ta = 25
C
200
ns
Output disable delay time
t
OD
Measurement circuit 3, Ta = 25
C
200
ns
Figure 1. PECL output waveform
Figure 2. OE timing waveform
t
r
t
f
OUTN
OUT
80%
20%
V
DD
2V
V
OH
V
SS
V
DD
t
W
t
PER
DUTY1 = (
t
W
/
t
PER
) 100
V
Opp
OE
t
OE
t
OD
V
DD
GND
V
DD
/2
V
DD
GND
OUT
OUTN
LOW-level
(High impedance)
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