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Электронный компонент: 100344F

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100344
Low Power 8-Bit Latch with Cut-Off Drivers
General Description
The 100344 contains eight D-type latches, individual inputs
(D
n
), outputs (Q
n
), a common enable pin (E), latch enable
(LE), and output enable pin (OEN). A Q output follows its D
input when both E and LE are LOW. When either E or LE (or
both) are HIGH, a latch stores the last valid data present on
its D input prior to E or LE going HIGH.
A HIGH on OEN holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is -2.0V, presenting a
high impedance to the data bus. This high impedance re-
duces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100344 outputs are designed to drive a doubly termi-
nated 50
transmission line (25
load impedance). All in-
puts have 50 k
pull-down resistors.
Features
n
Cut-off drivers
n
Drives 25
load
n
Low power operation
n
2000V ESD protection
n
Voltage compensated operating range = -4.2V to -5.7V
n
Available to MIL-STD-883
Logic Symbol
Pin Names
Description
D
0
D
7
Data Inputs
E
Enable Input
LE
Latch Enable Input
OEN
Output Enable Input
Q
0
Q
7
Data Outputs
Connection Diagrams
DS100317-4
24-Pin DIP
DS100317-1
24-Pin Quad Cerpak
DS100317-2
August 1998
100344
Low
Power
8-Bit
Latch
with
Cut-Off
Drivers
1998 National Semiconductor Corporation
DS100317
www.national.com
Logic Diagram
Truth Table
Inputs
Outputs
D
n
E
LE
OEN
Q
n
L
L
L
L
L
H
L
L
L
H
X
H
X
L
Latched (Note 1)
X
X
H
L
Latched (Note 1)
X
X
X
H
Cutoff
H = HIGH Voltage level
L = LOW Voltage level
Cutoff = lower-than-LOW state
X = Don't Care
Note 1: Retains data present before either LE or E go HIGH.
DS100317-5
www.national.com
2
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
V
EE
Pin Potential to Ground Pin
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output Current (DC Output HIGH)
-100 mA
ESD (Note 3)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 2: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to
(Notes 4, 5,
6)
+125C
-1085
-870
mV
-55C
V
IN
= V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-1830
-1620
mV
0C to
or V
IL
(Min)
25
to -2.0V
+125C
-1830
-1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to
(Notes 4, 5,
6)
+125C
-1085
mV
-55C
V
IN
= V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-1610
mV
0C to
or V
IL
(Max)
25
to -2.0V
+125C
-1555
mV
-55C
V
OLZ
Cutoff LOW Voltage
-1950
0C to
V
IN
= V
IH
(Min)
(Notes 4, 5,
6)
mV
+125C
or V
IL
(Max)
OEN = HIGH
-1850
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to
Guaranteed HIGH Signal
(Notes 4, 5,
6, 7)
+125C
for All Inputs
V
IL
Input LOW Voltage
-1830
-1475
mV
-55C to
Guaranteed LOW Signal
(Notes 4, 5,
6, 7)
+125C
for All Inputs
I
IL
Input LOW Current
0.50
A
-55C to
V
EE
= -4.2V
(Notes 4, 5,
6, 7)
+125C
V
IN
= V
IL
(Min)
I
IH
Input HIGH Current
240
A
0C to
V
EE
= -5.7V
(Notes 4, 5,
6)
+125C
V
IN
= V
IH
(Max)
340
A
-55C
I
EE
Power Supply Current
-55C to
Inputs Open
(Notes 4, 5,
6)
-195
-73
mA
+125C
V
EE
= -4.2V to -4.8V
-205
-73
V
EE
= -4.2V to -5.7V
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
www.national.com
3
AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.50
2.60
0.70
2.60
0.70
3.10
ns
Figures 1, 2
(Notes 8, 9,
10, 12)
t
PHL
D
n
to Output
t
PLH
Propagation Delay
0.80
3.30
1.00
3.30
1.10
3.80
ns
Figures 1, 4
(Notes 8, 9,
10, 12)
t
PHL
LE, E to Output
t
PZH
Propagation Delay
1.00
4.60
1.10
4.20
1.20
4.40
ns
Figures 1, 2
(Notes 8, 9,
10, 12)
t
PHZ
OEN to Output
0.70
3.00
0.70
2.80
0.70
3.20
t
TLH
Transition Time
0.40
2.50
0.40
2.40
0.40
2.70
ns
Figures 1, 3
(Note 11)
t
THL
20% to 80%, 80% to
20%
t
s
Setup Time
(Note 11)
D
0
D
7
1.50
1.50
1.70
ns
Figures 1, 3
t
h
Hold Time
(Note 11)
D
0
D
7
0.60
0.60
0.60
ns
Figures 1, 3
t
pw
(H)
Pulse Width HIGH
(Note 11)
LE, E
2.40
2.40
2.40
ns
Figures 1, 3
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures.
Note 9: Screen tested 100% on each device at +25C temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25C, Subgroup A9, and at +125C and -55C temperatures, Subgroups A10 and A11.
Note 11: Not tested at +25C, +125C, and -55C temperature (design characterization data).
Note 12: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Test Circuitry
DS100317-6
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1 and L2 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 25
to GND
C
L
= Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
www.national.com
4
Switching Waveforms
DS100317-7
FIGURE 2. Propagation Delay and Cutoff Times
DS100317-8
FIGURE 3. Setup, Hold and Pulse Width Times
DS100317-9
FIGURE 4. Propagation Delay LE, E to Q
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5