TL D 10833
NM27C256
262144-Bit
(32K
x
8
)
High
Performance
CMOS
EPROM
December 1993
NM27C256
262 144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The NM27C256 is a 256K Electrically Programmable Read
Only Memory It is manufactured in National's latest CMOS
split gate EPROM technology which enables it to operate at
speeds as fast as 120 ns access time over the full operating
range
The NM27C256 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software Its 120 ns access time
provides high speed operation with high-performance CPUs
The NM27C256 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment
Frequently-used software routines are quickly executed
from EPROM storage greatly enhancing system utility
The NM27C256 is configured in the standard EPROM pin-
out which provides an easy upgrade path for systems which
are currently using standard EPROMs
The NM27C256 is one member of a high density EPROM
Family which range in densities up to 4 Mb
Features
Y
High performance CMOS
120 ns access time
Y
JEDEC standard pin configuration
28-pin DIP package
32-pin chip carrier
Y
Drop-in replacement for 27C256 or 27256
Y
Manufacturer's identification code
Block Diagram
TL D 10833 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
HPC
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M65 Printed in U S A
Connection Diagrams
27C080 27C040 27C020 27C010 27C512
A19
XX V
PP
XX V
PP
XX V
PP
A16
A16
A16
A16
A15
A15
A15
A15
A15
A12
A12
A12
A12
A12
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
O0
O0
O0
O0
O0
O1
O1
O1
O1
O1
O2
O2
O2
O2
O2
GND
GND
GND
GND
GND
DIP
NM27C256
TL D 10833 2
27C512 27C010 27C020 27C040 27C080
V
CC
V
CC
V
CC
V
CC
XX PGM XX PGM
A18
A18
V
CC
XX
A17
A17
A17
A14
A14
A14
A14
A14
A13
A13
A13
A13
A13
A8
A8
A8
A8
A8
A9
A9
A9
A9
A9
A11
A11
A11
A11
A11
OE V
PP
OE
OE
OE
OE V
PP
A10
A10
A10
A10
A10
CE PGM
CE
CE
CE PGM CE PGM
O7
O7
O7
O7
O7
O6
O6
O6
O6
O6
O5
O5
O5
O5
O5
O4
O4
O4
O4
O4
O3
O3
O3
O3
O3
Note
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins
Commercial Temp Range (0 C to
a
70 C)
V
CC
e
5V
g
10%
Parameter Order Number
Access Time (ns)
NM27C256 Q N V 120
120
NM27C256 Q N V 150
150
NM27C256 Q N V 200
200
Military Temp Range (
b
55 C to
a
125 C)
V
CC
e
5V
g
10%
Parameter Order Number
Access Time (ns)
NM27C256 QM 150
150
NM27C256 QM 250
250
Extended Temp Range (
b
40 C to
a
85 C)
V
CC
e
5V
g
10%
Parameter Order Number
Access Time (ns)
NM27C256 QE NE VE 120
120
NM27C256 QE NE VE 150
150
NM27C256 QE NE VE 200
200
Note
Surface mount PLCC package available for commercial and extended
temperature ranges only
Package Types NM27C256 Q N V XXX
Q
e
Quartz-Windowed Ceramic DIP
N
e
Plastic OTP DIP
V
e
Surface-Mount PLCC
All packages conform to the JEDEC standard
All versions are guaranteed to function for slower
speeds
Pin Names
Symbol
Description
A0 A14
Addresses
CE
Chip Enable
OE
Output Enable
O0 O7
Outputs
PGM
Program
XX
Don't Care (during Read)
PLCC
TL D 10833 3
Top
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
All Input Voltages except A9 with
Respect to Ground
b
0 6V to
a
7V
V
PP
and A9 with Respect
to Ground
b
0 7V to
a
14V
V
CC
Supply Voltage with
Respect to Ground
b
0 6V to
a
7V
ESD Protection
l
2000V
All Output Voltages with
Respect to Ground
V
CC
a
1 0V to GND
b
0 6V
Operating Range
Range
Temperature
V
CC
Comm'l
0 C to
a
70 C
a
5V
g
10%
Industrial
b
40 C to
a
85 C
a
5V
g
10%
Military
b
55 C to
a
125 C
a
5V
g
10%
Read Operation
DC Electrical Characteristics
Over Operating Range with V
PP
e
V
CC
Symbol
Parameter
Test Conditions
Min
Max
Units
V
IL
Input Low Level
b
0 5
0 8
V
V
IH
Input High Level
2 0
V
CC
a
1
V
V
OL
Output Low Voltage
I
OL
e
2 1 mA
0 4
V
V
OH
Output High Voltage
I
OH
e b
2 5 mA
3 5
V
I
SB1
V
CC
Standby Current
CE
e
V
CC
g
0 3V
100
m
A
(Note 11)
(CMOS)
I
SB2
V
CC
Standby Current (TTL)
CE
e
V
IH
1
mA
I
CC1
V
CC
Active Current
CE
e
OE
e
V
IL
f
e
5 MHz
35
mA
TTL Inputs
Inputs
e
V
IH
or V
IL
I O
e
0 mA
I
PP
V
PP
Supply Current
V
PP
e
V
CC
10
m
A
V
PP
V
PP
Read Voltage
V
CC
b
0 7
V
CC
V
I
LI
Input Load Current
V
IN
e
5 5V or GND
b
1
1
m
A
I
LO
Output Leakage Current
V
OUT
e
5 5V or GND
b
10
10
m
A
AC Electrical Characteristics
Over Operating Range with V
PP
e
V
CC
Symbol
Parameter
100
120
150
200
Units
Min
Max
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
100
120
150
200
ns
t
CE
CE to Output Delay
100
120
150
200
t
OE
OE to Output Delay
50
50
50
50
t
DF
Output Disable to
30
35
45
55
(Note 2)
Output Float
t
OH
Output Hold from Addresses
(Note 2)
CE or OE
0
0
0
0
Whichever Occurred First
3
Capacitance
T
A
e a
25 C f
e
1 MHz (Note 2)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
e
0V
6
12
pF
C
OUT
Output Capacitance
V
OUT
e
0V
9
12
pF
AC Test Conditions
Output Load
1 TTL Gate and
C
L
e
100 pF (Note 8)
Input Rise and Fall Times
s
5 ns
Input Pulse Levels
0 45 to 2 4V
Timing Measurement Reference Level
(Note 10)
Inputs
0 8V and 2 0V
Outputs
0 8V and 2 0V
AC Waveforms
(Notes 6 7 and 9)
TL D 10833 4
Note 1
Stresses above those listed under ``Absolute Maximum Ratings'' may cause permanent damage to the device This is stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
This parameter is only sampled and is not 100% tested
Note 3
OE may be delayed up to t
ACC
b
t
OE
after the falling edge of CE without impacting t
ACC
Note 4
The t
DF
and t
CF
compare level is determined as follows
High to TRI-STATE
the measured V
OH1
(DC)
b
0 10V
Low to TRI-STATE the measured V
OL1
(DC)
a
0 10V
Note 5
TRI-STATE may be attained using OE or CE
Note 6
The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 0 1 mF ceramic capacitor be used on
every device between V
CC
and GND
Note 7
The outputs must be restricted to V
CC
a
1 0V to avoid latch-up and device damage
Note 8
TTL Gate I
OL
e
1 6 mA I
OH
e b
400 mA
C
L
e
100 pF includes fixture capacitance
Note 9
V
PP
may be connected to V
CC
except during programming
Note 10
Inputs and outputs can undershoot to
b
2 0V for 20 ns Max
Note 11
CMOS inputs V
IL
e
GND
g
0 3V V
IH
e
V
CC
g
0 3V
4
Programming Characteristics
(Notes 1 2 3 4 and 5)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
AS
Address Setup Time
1
m
s
t
OES
OE Setup Time
1
m
s
t
VPS
V
PP
Setup Time
1
m
s
t
VCS
V
CC
Setup Time
1
m
s
t
DS
Data Setup Time
1
m
s
t
AH
Address Hold Time
0
m
s
t
DH
Data Hold Time
1
m
s
t
DF
Output Enable to Output
CE
e
V
IL
0
60
ns
Float Delay
t
PW
Program Pulse Width
95
100
105
m
s
t
OE
Data Valid from OE
CE
e
V
IL
100
ns
I
PP
V
PP
Supply Current
CE
e
V
IL
30
mA
during Programming Pulse
I
CC
V
CC
Supply Current
50
mA
T
A
Temperature Ambient
20
25
30
C
V
CC
Power Supply Voltage
6 0
6 25
6 5
V
V
PP
Programming Supply Voltage
12 5
12 75
13 0
V
t
FR
Input Rise Fall Time
5
ns
V
IL
Input Low Voltage
0 0
0 45
V
V
IH
Input High Voltage
2 4
4 0
V
t
IN
Input Timing Reference Voltage
0 8
2 0
V
t
OUT
Output Timing Reference Voltage
0 8
2 0
V
Programming Waveforms
(Note 3)
TL D 10833 5
Note 1
National's standard product warranty applies to devices programmed to specifications described herein
Note 2
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
The EPROM must not be inserted into or removed from a
board with voltage applied to V
PP
or V
CC
Note 3
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V Care must be taken when switching the V
PP
supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across V
PP
V
CC
to GND to suppress
spurious voltage transients which may damage the device
Note 4
Programming and program verify are tested with the Fast Program Algorithm at typical power supply voltages and timings
Note 5
During power up the PGM pin must be brought high (
t
V
IH
) either coincident with or before power is applied to V
PP
5
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