Document Outline

• List of Figures
  • Figure 1-1. Internal Block Diagram
  • Figure 1-2. Geode� GXm/CS5530 System Block Diagram
  • Figure 1-3. CS9210 Interface System Diagram
  • Figure 2-1. Functional Block Diagram
  • Figure 2-2. 352 BGA Pin Assignment Diagram
  • Figure 2-3. 320 SPGA Pin Assignment Diagram
  • Figure 2-4. Subsystem Signal Connections
  • Figure 2-5. PIXEL Signal Connections
  • Figure 2-6. BGA Recommended Split Power Plane and Decoupling
  • Figure 2-7. SPGA Recommended Split Power Plane and Decoupling
  • Figure 3-1. CPU Cache Architecture
  • Figure 3-2. Memory and I/O Address Spaces
  • Figure 3-3. Offset Address Calculation
  • Figure 3-4. Real Mode Address Calculation
  • Figure 3-5. Protected Mode Address Calculation
  • Figure 3-6. Selector Mechanisms
  • Figure 3-7. Selector Mechanism Caching
  • Figure 3-8. Paging Mechanism
  • Figure 3-9. System Management Memory Address Space
  • Figure 3-10. SMM Execution Flow
  • Figure 3-11. SMI Nesting State Machine
  • Figure 3-12. SMM and Suspend Mode State Diagram
  • Figure 4-1. Internal Block Diagram
  • Figure 4-2. Geode� GXm Processor Memory Space
  • Figure 4-3. Memory Controller Block Diagram
  • Figure 4-4. Memory Array Configuration
  • Figure 4-5. Basic Read Cycle with a CAS Latency of Two
  • Figure 4-6. Basic Write Cycle
  • Figure 4-7. Auto Refresh Cycle
  • Figure 4-8. Read/WRT Command to a New Row Address
  • Figure 4-9. SDCLKIN Clocking
  • Figure 4-10. Effects of SHFTSDCLK Programming Bits Example
  • Figure 4-11. Graphics Pipeline Block Diagram
  • Figure 4-12. Example of Monochrome Patterns
  • Figure 4-13. Example of Dither Patterns
  • Figure 4-14. Display Controller Block Diagram
  • Figure 4-15. Pixel Arrangement Within a DWORD
  • Figure 4-16. Display Controller Signal Connections
  • Figure 4-17. Video Port Data Transfer (CS5530)
  • Figure 4-18. Basic Read Operation
  • Figure 4-19. Basic Write Operation
  • Figure 4-20. Basic Arbitration
  • Figure 6-1. SUSP#-Initiated Suspend Mode
  • Figure 6-2. HALT-Initiated Suspend Mode
  • Figure 6-3. PCI Access During Suspend Mode
  • Figure 6-4. Stopping SYSCLK During Suspend Mode
  • Figure 7-1. Drive Level and Measurement Points for Switching Characteristics
  • Figure 7-2. DCLK Timing and Measurement Points
  • Figure 7-3. SDCLK, SDCLK[3:0] Timing and Measurement Points
  • Figure 7-4. Output Timing
  • Figure 7-5. Input Timing
  • Figure 7-6. Output Valid Timing
  • Figure 7-7. Setup and Hold Timings - Read Data In
  • Figure 7-8. Graphics Port Timing
  • Figure 7-9. Video Port Timing
  • Figure 7-10. DCLK Timing
  • Figure 7-11. TCK Timing and Measurement Points
  • Figure 7-12. JTAG Test Timings
  • Figure 8-1. Heatsink Example
  • Figure 8-2. 352-Terminal BGA Mechanical Package Outline
  • Figure 8-3. 320-Pin SPGA Mechanical Package Outline
• List of Tables
  • Table 2-1. Pin Type Definitions
  • Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number
  • Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name
  • Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number
  • Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name
  • Table 3-1. Initialized Core Register Controls 
  • Table 3-2. Application Register Set
  • Table 3-3. Segment Register Selection Rules
  • Table 3-4. EFLAGS Register
  • Table 3-5. System Register Set
  • Table 3-6. Control Registers Map
  • Table 3-7. CR4-CR0 Bit Definitions 
  • Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits
  • Table 3-9. Configuration Register Summary
  • Table 3-10. Configuration Register Map
  • Table 3-11. Configuration Registers 
  • Table 3-12. Debug Registers
  • Table 3-13. DR7 and DR6 Bit Definitions
  • Table 3-14. TLB Test Registers
  • Table 3-15. TR7-TR6 Bit Definitions 
  • Table 3-16. Cache Test Registers
  • Table 3-17. TR5-TR3 Bit Definitions
  • Table 3-18. Cache Test Operations
  • Table 3-19. Memory Addressing Modes
  • Table 3-20. GDTR, LDTR and IDTR Registers
  • Table 3-21. Application and System Segment Descriptors
  • Table 3-22. Application and System Segment Descriptors Bit Definitions 
  • Table 3-23. Application and System Segment Descriptors TYPE Bit Definitions 
  • Table 3-24. Gate Descriptors
  • Table 3-25. Gate Descriptors Bit Definitions
  • Table 3-26. 32-Bit Task State Segment (TSS) Table
  • Table 3-27. 16-Bit Task State Segment (TSS) Table
  • Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)
  • Table 3-29. Interrupt Vector Assignments
  • Table 3-30. Interrupt and Exception Priorities
  • Table 3-31. Exception Changes in Real Mode
  • Table 3-32. Error Codes
  • Table 3-33. Error Code Bit Definitions
  • Table 3-34. SMI# and SMINT Recognition Requirements
  • Table 3-35. SMM Memory Space Header
  • Table 3-36. SMM Memory Space Header Description
  • Table 3-37. SMM Instruction Set
  • Table 3-38. Descriptor Types Used for Control Transfer
  • Table 3-39. FPU Registers
  • Table 4-1. GCR Register
  • Table 4-2. Display Resolution Skip Counts
  • Table 4-3. L1 Cache BitBLT Register Summary
  • Table 4-4. L1 Cache BitBLT Registers
  • Table 4-5. Scratchpad Organization
  • Table 4-6. Display Driver Instructions
  • Table 4-7. CPU-Access Instructions
  • Table 4-8. Address Map for CPU-Access Registers
  • Table 4-9. Internal Bus Interface Unit Register Summary
  • Table 4-10. Internal Bus Interface Unit Registers
  • Table 4-11. Region-Control-Field Bit Definitions
  • Table 4-12. Synchronous DRAM Configurations
  • Table 4-13. Basic Command Truth Table
  • Table 4-14. Address Line Programming during MRS Cycles
  • Table 4-15. Memory Controller Register Summary
  • Table 4-16. Memory Controller Registers 
  • Table 4-17. Auto LOI -- 2 DIMMs, Same Size, 1 DIMM Bank
  • Table 4-18. Auto LOI -- 2 DIMMs, Same Size, 2 DIMM Banks
  • Table 4-19. Non-Auto LOI -- 1 or 2 DIMMs, Different Sizes, 1 DIMM Bank
  • Table 4-20. Non-Auto LOI -- 1 or 2 DIMMs, Different Sizes, 2 DIMM Banks
  • Table 4-21. Graphics Pipeline Registers
  • Table 4-22. GP_RASTER_MODE Bit Patterns
  • Table 4-23. Common Raster Operations
  • Table 4-24. Graphics Pipeline Configuration Register Summary 
  • Table 4-25. Graphics Pipeline Configuration Registers 
  • Table 4-26. TFT Panel Display Modes
  • Table 4-27. TFT Panel Data Bus Formats
  • Table 4-28. CRT Display Modes
  • Table 4-29. Display Controller Register Summary 
  • Table 4-30. Display Controller Configuration and Status Registers 
  • Table 4-31. Display Controller Memory Organization Registers 
  • Table 4-32. Display Controller Timing Registers 
  • Table 4-33. Display Controller Cursor Position Registers 
  • Table 4-34. Display Controller Color Registers
  • Table 4-35. Display Controller Palette and RAM Diagnostic Registers
  • Table 4-36. Special-Cycle Code to CONFIG_ADDRESS
  • Table 4-37. PCI Configuration Registers
  • Table 4-38. Format for Accessing the Internal PCI Configuration Registers
  • Table 4-39. PCI Configuration Space Register Summary
  • Table 4-40. PCI Configuration Registers 
  • Table 5-1. Standard VGA Modes
  • Table 5-2. VGA Configuration Registers Summary
  • Table 5-3. VGA Configuration Registers
  • Table 5-4. Virtual VGA Register Summary
  • Table 5-5. Virtual VGA Registers
  • Table 6-1. Power Management Register Summary 
  • Table 6-2. Power Management Control and Status Registers 
  • Table 6-3. Power Management Programmable Address Region Registers
  • Table 7-1. Part Numbers
  • Table 7-2. Pins with 20-kohm Internal Resistor
  • Table 7-3. Absolute Maximum Ratings
  • Table 7-4. Operating Conditions
  • Table 7-5. DC Characteristics
  • Table 7-6. Drive Level and Measurement Points for Switching Characteristics
  • Table 7-7. Clock Signals
  • Table 7-8. System Signals
  • Table 7-9. PCI Interface Signals
  • Table 7-10. SDRAM Interface Signals
  • Table 7-11. Video Interface Signals
  • Table 7-12. JTAG AC Specification
  • Table 8-1. Junction-to-Case Thermal Resistance for SPGA and BGA Packages
  • Table 8-2. Case-to-Ambient Thermal Resistance Examples @ 85C
  • Table 8-3. Mechanical Package Outline Legend
  • Table 9-1. General Instruction Set Format
  • Table 9-2. Instruction Fields
  • Table 9-3. Instruction Prefix Summary
  • Table 9-4. w Field Encoding
  • Table 9-5. d Field Encoding
  • Table 9-6. s Field Encoding
  • Table 9-7. eee Field Encoding
  • Table 9-8. General Registers Selected by mod r/m Fields and w Field
  • Table 9-9. mod r/m Field Encoding
  • Table 9-10. General Registers Selected by reg Field
  • Table 9-11. sreg2 Field Encoding
  • Table 9-12. sreg3 Field Encoding
  • Table 9-13. ss Field Encoding
  • Table 9-14. index Field Encoding
  • Table 9-15. mod base Field Encoding
  • Table 9-16. CPUID Levels Summary
  • Table 9-17. CPUID Data Returned when EAX = 0
  • Table 9-18. EAX, EBX, ECX CPUID Data Returned when EAX = 1
  • Table 9-19. EDX CPUID Data Returned when EAX = 1
  • Table 9-20. Standard CPUID with EAX = 00000002h
  • Table 9-21. Maximum Extended CPUID Level
  • Table 9-22. EAX, EBX, ECX CPUID Data Returned when EAX = 80000001h
  • Table 9-23. EDX CPUID Data Returned when EAX = 80000001h
  • Table 9-24. Official CPU Name
  • Table 9-25. Standard CPUID with EAX = 80000005h
  • Table 9-26. Processor Core Instruction Set Table Legend
  • Table 9-27. Processor Core Instruction Set Summary 
  • Table 9-28. FPU Instruction Set Table Legend
  • Table 9-29. FPU Instruction Set Summary 
  • Table 9-30. MMX Instruction Set Table Legend
  • Table 9-31. MMX Instruction Set Summary 
  • Table 9-32. Extend MMX Instruction Set Table Legend
  • Table 9-33. Extended MMX Instruction Set Summary 
  • Table A-1. Revision History
  • Table A-2. Edits to Current Revision
• 1.0 Architecture Overview
  • 1.1 Integer Unit
  • 1.2 Floating Point Unit
  • 1.3 Write-Back Cache Unit
  • 1.4 Memory Management Unit
    • 1.4.1 Internal Bus Interface Unit
  • 1.5 Integrated Functions
    • 1.5.1 Graphics Accelerator
    • 1.5.2 Display Controller
    • 1.5.3 XpressRAM Memory Subsystem
    • 1.5.4 PCI Controller
  • 1.6 Geode GXM/CS5530 System Designs
• 2.0 Signal Definitions
  • 2.1 Pin Assignments
  • 2.2 Signal Descriptions
    • 2.2.1 System Interface Signals 
    • 2.2.2 PCI Interface Signals 
    • 2.2.3 Memory Controller Interface Signals 
    • 2.2.4 Video Interface Signals 
    • 2.2.5 Power, Ground, and No Connect Signals 
    • 2.2.6 Internal Test and Measurement Signals
  • 2.3 Subsystem Signal Connections
  • 2.4 Power Planes
• 3.0 Processor Programming
  • 3.1 Core Processor Initialization
  • 3.2 Instruction Set Overview
    • 3.2.1 Lock Prefix
  • 3.3 Register Sets
    • 3.3.1 Application Register Set
      • 3.3.1.1 General Purpose Registers
      • 3.3.1.2 Segment Registers
      • 3.3.1.3 Instruction Pointer Register
      • 3.3.1.4 EFLAGS Register
    • 3.3.2 System Register Set
      • 3.3.2.1 Control Registers
      • 3.3.2.2 Configuration Registers
      • 3.3.2.3 Debug Registers
      • 3.3.2.4 Test Registers
    • 3.3.3 Model Specific Register Set
    • 3.3.4 Time Stamp Counter
  • 3.4 Address Spaces
    • 3.4.1 I/O Address Space
    • 3.4.2 Memory Address Space
  • 3.5 Offset, Segment, and Paging Mechanisms
  • 3.6 Offset Mechanism
  • 3.7 Descriptors and Segment Mechanisms
    • 3.7.1 Real and Virtual 8086 Mode Segment Mechanisms
    • 3.7.2 Segment Mechanism in Protective Mode
      • 3.7.2.1 Segment Selectors
    • 3.7.3 GDTR and LDTR Registers
      • 3.7.3.1 Segment Descriptors
      • 3.7.3.2 Task, Gate and Interrupt Descriptors
    • 3.7.4 Descriptor Bit Structure
    • 3.7.5 Gate Descriptors
  • 3.8 Multitasking and Task State Segments
  • 3.9 Paging Mechanism
  • 3.10 Interrupts and Exceptions
    • 3.10.1 Interrupts
    • 3.10.2 Exceptions
    • 3.10.3 Interrupt Vectors
      • 3.10.3.1 Interrupt Vector Assignments
      • 3.10.3.2 Interrupt Descriptor Table
    • 3.10.4 Interrupt and Exception Priorities
    • 3.10.5 Exceptions in Real Mode
    • 3.10.6 Error Codes
  • 3.11 System Management Mode
    • 3.11.1 SMM Enhancements
    • 3.11.2 SMM Operation
    • 3.11.3 The SMI# Pin
    • 3.11.4 SMM Configuration Registers
    • 3.11.5 SMM Memory Space Header
    • 3.11.6 SMM Instructions
    • 3.11.7 SMM Memory Space
    • 3.11.8 SMI Generation
    • 3.11.9 SMI Service Routine Execution
      • 3.11.9.1 SMI Nesting
      • 3.11.9.2 CPU States Related to SMM and Suspend Mode
  • 3.12 Shutdown and Halt
  • 3.13 Protection
    • 3.13.1 Privilege Levels
    • 3.13.2 I/O Privilege Levels
    • 3.13.3 Privilege Level Transfers
      • 3.13.3.1 Gates
    • 3.13.4 Initialization and Transition to Protected Mode
  • 3.14 Virtual 8086 Mode
    • 3.14.1 Memory Addressing
    • 3.14.2 Protection
    • 3.14.3 Interrupt Handling
    • 3.14.4 Entering and Leaving Virtual 8086 Mode
  • 3.15 Floating Point Unit Operations
    • 3.15.1 FPU (Floating Point Unit) Register Set
    • 3.15.2 FPU Tag Word Register
    • 3.15.3 FPU Status Register
    • 3.15.4 FPU Mode Control Register
• 4.0 Integrated Functions
  • 4.1 Integrated Functions Programming Interface
    • 4.1.1 Graphics Control Register
    • 4.1.2 Control Registers
    • 4.1.3 Graphics Memory
    • 4.1.4 L1 Cache Controller
      • 4.1.4.1 Scratchpad Memory
    • 4.1.5 Display Driver Instructions
    • 4.1.6 CPU_READ/CPU_WRITE Instructions
  • 4.2 Internal Bus Interface Unit
    • 4.2.1 FPU Error Support
    • 4.2.2 A20M Support
    • 4.2.3 SMI Generation
    • 4.2.4 640 KB to 1 MB Region
    • 4.2.5 Internal Bus Interface Unit Registers
  • 4.3 Memory Controller
    • 4.3.1 Memory Array Configuration
    • 4.3.2 Memory Organizations
    • 4.3.3 SDRAM Commands
      • 4.3.3.1 SDRAM Initialization Sequence
    • 4.3.4 Memory Controller Register Description
    • 4.3.5 Address Translation
      • 4.3.5.1 High Order Interleaving
      • 4.3.5.2 Low Order Interleaving
      • 4.3.5.3 Physical Address to DRAM Address Conversion
    • 4.3.6 Memory Cycles
    • 4.3.7 SDRAM Interface Clocking
  • 4.4 Graphics Pipeline
    • 4.4.1 BitBLT/Vector Engine
    • 4.4.2 Master/Slave Registers
    • 4.4.3 Pattern Generation
      • 4.4.3.1 Monochrome Patterns
      • 4.4.3.2 Dither Patterns
      • 4.4.3.3 Color Patterns
    • 4.4.4 Source Expansion
    • 4.4.5 Raster Operations
    • 4.4.6 Graphics Pipeline Register Descriptions
  • 4.5 Display Controller
    • 4.5.1 Display FIFO
    • 4.5.2 Compression Technology
    • 4.5.3 Motion Video Acceleration Support
    • 4.5.4 Hardware Cursor
    • 4.5.5 Display Timing Generator
    • 4.5.6 Dither and Frame-Rate Modulation
    • 4.5.7 Display Modes
    • 4.5.8 Graphics Memory Map
      • 4.5.8.1 DC Memory Organization Registers
      • 4.5.8.2 Frame Buffer and Compression Buffer Organization
      • 4.5.8.3 VGA Display Support
      • 4.5.8.4 Cursor Pattern Memory Organization
    • 4.5.9 Display Controller Registers
      • 4.5.9.1 Configuration and Status Registers
    • 4.5.10 Memory Organization Registers
    • 4.5.11 Timing Registers
    • 4.5.12 Cursor Position Registers
    • 4.5.13 Color Registers
    • 4.5.14 Palette Access Registers
    • 4.5.15 CS5530 Display Controller Interface
      • 4.5.15.1 CS5530 Video Port Data Transfer
  • 4.6 PCI Controller
    • 4.6.1 X-Bus PCI Slave
    • 4.6.2 X-Bus PCI Master
    • 4.6.3 PCI Arbiter
    • 4.6.4 Generating Configuration Cycles
    • 4.6.5 Generating Special Cycles
    • 4.6.6 PCI Configuration Space Control Registers
    • 4.6.7 PCI Configuration Space Registers
    • 4.6.8 PCI Cycles
      • 4.6.8.1 PCI Read Transaction
      • 4.6.8.2 PCI Write Transaction
      • 4.6.8.3 PCI Arbitration
      • 4.6.8.4 PCI Halt Command
• 5.0 Virtual Subsystem Architecture
  • 5.1 Virtual VGA
    • 5.1.1 Traditional VGA Hardware
      • 5.1.1.1 VGA Memory Organization
      • 5.1.1.2 VGA Front End
      • 5.1.1.3 Address Mapping
  • 5.2 GXm Virtual VGA
    • 5.2.1 Datapath Elements
    • 5.2.2 Video Refresh
    • 5.2.3 GXm VGA Hardware
      • 5.2.3.1 SMI Generation
      • 5.2.3.2 VGA Memory Addresses
      • 5.2.3.3 VGA Configuration Registers
      • 5.2.3.4 VGA Control Register
      • 5.2.3.5 VGA Mask Registers
      • 5.2.3.6 VGA Range Detection
      • 5.2.3.7 VGA Sequencer
      • 5.2.3.8 VGA Write/Read Path
      • 5.2.3.9 VGA Address Generator
      • 5.2.3.10 VGA Memory
    • 5.2.4 VGA Video BIOS
    • 5.2.5 Virtual VGA Register Descriptions
• 6.0 Power Management
  • 6.1 APM Support
  • 6.2 CPU Suspend Command Registers
  • 6.3 Suspend Modulation
  • 6.4 3-Volt Suspend Mode
  • 6.5 Suspend Mode and Bus Cycles
    • 6.5.1 Initiating Suspend with SUSP#
    • 6.5.2 Initiating Suspend with HALT
    • 6.5.3 Responding to a PCI Access During Suspend Mode
    • 6.5.4 Stopping the Input Clock
  • 6.6 GXm Processor Serial Bus
    • 6.6.1 Serial Packet Transmission
  • 6.7 Power Management Registers
• 7.0 Electrical Specifications
  • 7.1 Part Numbers
  • 7.2 Electrical Connections
    • 7.2.1 Power/Ground Connections and Decoupling
    • 7.2.2 Power Sequencing the Core and I/O Voltages
    • 7.2.3 NC-Designated Pins
    • 7.2.4 Pull-Up and Pull-Down Resistors
    • 7.2.5 Unused Input Pins
  • 7.3 Absolute Maximum Ratings
  • 7.4 Operating Conditions
  • 7.5 DC Characteristics
  • 7.6 AC Characteristics
• 8.0 Package Specifications
  • 8.1 Thermal Characteristics
    • 8.1.1 Heatsink Considerations
  • 8.2 Mechanical Package Outlines
• 9.0 Instruction Set
  • 9.1 General Instruction Set Format
    • 9.1.1 Prefix (Optional)
    • 9.1.2 Opcode
      • 9.1.2.1 w Field (Operand Size)
      • 9.1.2.2 d Field (Operand Direction)
      • 9.1.2.3 s Field (Immediate Data Field Size)
      • 9.1.2.4 eee Field (MOV-Instruction Register Selection)
    • 9.1.3 mod and r/m Byte (Memory Addressing)
    • 9.1.4 reg Field
      • 9.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)
      • 9.1.4.2 sreg3 Field (FS and GS Segment Register Selection)
    • 9.1.5 s-i-b Byte (Scale, Indexing, Base)
      • 9.1.5.1 ss Field (Scale Selection)
      • 9.1.5.2 index Field (Index Selection)
      • 9.1.5.3 Base Field (s-i-b Present)
  • 9.2 CPUID Instruction
    • 9.2.1 Standard CPUID Levels
      • 9.2.1.1 CPUID Instruction with EAX = 00000000h
      • 9.2.1.2 CPUID Instruction with EAX = 00000001h
      • 9.2.1.3 CPUID Instruction with EAX = 00000002h
    • 9.2.2 Extended CPUID Levels
      • 9.2.2.1 CPUID Instruction with EAX = 8000000h
      • 9.2.2.2 CPUID Instruction with EAX = 8000 0001h
      • 9.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, 80000004h
      • 9.2.2.4 CPUID Instruction with EAX = 80000005h
  • 9.3 Processor Core Instruction Set
  • 9.4 FPU Instruction Set
  • 9.5 MMX Instruction Set
  • 9.6 National Semiconductor Extended MMX Instruction Set
• Appendix A Support Documentation
  • A.1 Order Information
  • A.2 Data Book Revision History