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Электронный компонент: 54ABT273J-QML

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54ABT273
Octal D-Type Flip-Flop
General Description
The 'ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
Buffered, asynchronous Master Reset
n
See 'ABT377 for clock enable version
n
See 'ABT373 for transparent latch version
n
See 'ABT374 for TRI-STATE
version
n
Output sink capability of 48 mA, source capability of
24 mA
n
Guaranteed latchup protection
n
High impedance glitch free bus loading during entire
power up and power down cycle
n
Non-destructive hot insertion capability
n
Disable time less than enable time to avoid bus
contention
n
Standard Microcircuit Drawing (SMD) 5962-9321701
Ordering Code
Military
Package
Package Description
Number
54ABT273J-QML
J20A
20-Lead Ceramic Dual-In-Line
54ABT273W-QML
W20A
20-Lead Cerpack
54ABT273E-QML
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
July 1998
54ABT273
Octal
D-T
ype
Flip-Flop
1998 National Semiconductor Corporation
DS100205
www.national.com
Connection Diagrams
Pin
Description
Names
D
0
D
7
Data Inputs
MR
Master Reset
(Active LOW)
CP
Clock Pulse Input
(Active Rising Edge)
Q
0
Q
7
Data Outputs
Truth Table
Mode Select-Function Table
Operating Mode
Inputs
Output
MR
CP
D
n
Q
n
Reset (Clear)
L
X
X
L
Load "1"
H
N
h
H
Load "0"
H
N
l
L
H = HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
sition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
sition
X = Immaterial
N
= LOW-to-HIGH clock transition
Logic Diagram
Pin Assignment for DIP
and Flatpack
DS100205-1
Pin Assignment
for LCC
DS100205-2
DS100205-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-0.5V to +4.75V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
(Across Comm Operating Range)
Over Voltage Latchup
V
CC
+ 4.5V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT273
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54ABT
2.5
I
OH
= -3 mA
54ABT
2.0
V
Min
I
OH
= -24 mA
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Note 4)
5
V
IN
= V
CC
I
BVI
Input HIGH Current
7
A
Max
V
IN
= 7.0V
Breakdown Test
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Note 4)
-5
V
IN
= 0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A
All Other Pins Grounded
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0.0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
= V
CC
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCT
Maximum I
CC
/Input
Outputs Enabled
V
I
= V
CC
- 2.1V
1.5
mA
Max
Data Input V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
0.3
mA/
Max
Outputs Open (Note 3)
MHz
One Bit Toggling, 50% Duty Cycle
Note 3: For 8 bits toggling, I
CCD
<
0.5 mA/MHz.
Note 4: Guaranteed but not tested.
3
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AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
f
max
Max Clock
150
MHz
Frequency
t
PLH
Propagation Delay
1.0
7.0
ns
t
PHL
CP to O
n
1.0
7.5
t
PHL
Propagation Delay
1.0
8.2
ns
MR to O
n
AC Operating Requirements
54ABT
T
A
= -55C to +125C
Symbol
Parameter
V
CC
= 4.5V to 5.5V
Units
C
L
= 50 pF
Min
Max
t
s
(H)
Setup Time, HIGH
2.0
ns
t
s
(L)
or LOW D
n
to CP
2.5
t
h
(H)
Hold Time, HIGH
1.4
ns
t
h
(L)
or LOW D
n
to CP
1.4
t
w
(H)
Pulse Width, CP,
3.3
ns
t
w
(L)
HIGH or LOW
3.3
t
w
(L)
Master Reset Pulse
3.3
ns
Width, LOW
t
REC
Recovery Time
2.0
ns
MR to CP
Capacitance
Symbol
Parameter
Typ
Units
Conditions
T
A
= 25C
C
IN
Input Capacitance
5
pF
V
CC
= 0V
C
OUT
(Note 5)
Output Capacitance
9
pF
V
CC
= 5.0V
Note 5: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-833B, Method 3012.
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4
AC Loading
DS100205-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100205-5
FIGURE 2. Propagation Delay,
Pulse Width Waveforms
DS100205-6
FIGURE 3. V
M
= 1.5V
Input Pulse Requirements
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 4. Test Input Signal Requirements
DS100205-8
FIGURE 5. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100205-9
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
5
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