54ABT573
Octal D-Type Latch with TRI-STATE
Outputs
General Description
The 'ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE) in-
puts.
This device is functionally identical to the 'ABT373 but has
different pinouts.
Features
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
Functionally identical to 'ABT373
n
TRI-STATE outputs for bus interfacing
n
Output sink capability of 48 mA, source capability of
24 mA
n
Output switching specified for both 50 pF and 250 pF
loads
n
Guaranteed latchup protection
n
High impedance glitch-free bus loading during entire
power up and power down
n
Nondestructive hot insertion capability
n
Standard Microcircuit Drawing (SMD) 5962-9321901
Ordering Code
Military
Package
Package Description
Number
54ABT573J-QML
J20A
20-Lead Ceramic Dual-In-Line
54ABT573W-QML
W20A
20-Lead Cerpack
54ABT573E-QML
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
TRI-STATE Output Enable Input
(Active LOW)
O
0
O
7
TRI-STATE Latch Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Pin Assignment
for DIP and Cerpack
DS100219-1
Pin Assignment
for LCC
DS100219-39
July 1998
54ABT573
Octal
D-T
ype
Latch
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100219
www.national.com
Functional Description
The 'ABT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Function Table
Inputs
Outputs
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
O
0
H
X
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O
0
= Value stored from previous clock cycle
Logic Diagram
DS100219-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-0.5V to +5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
Twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT573
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54ABT
2.5
V
Min
I
OH
= -3 mA
54ABT
2.0
I
OH
= -24 mA
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Note 4)
5
V
IN
= V
CC
I
BVI
Input HIGH Current
7
A
Max
V
IN
= 7.0V
Breakdown Test
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Note 4)
-5
V
IN
= 0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current
50
A
0 - 5.5V
V
OUT
= 2.7V; OE = 2.0V
I
OZL
Output Leakage Current
-50
A
0 - 5.5V
V
OUT
= 0.5V; OE = 2.0V
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0.0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
= V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE = V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
2.5
mA
V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Max
Enable Input V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Data Input V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open
(Note 4)
0.12
MHz
OE = GND, LE = V
CC
(Note 3)
One Bit Toggling, 50% Duty Cycle
Note 3: For 8 bits toggling, I
CCD
<
0.8 mA/MHz.
Note 4: Guaranteed but not tested.
3
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DC Electrical Characteristics
Symbol
Parameter
Min
Max
Units
V
CC
Conditions
C
L
= 50 pF, R
L
= 500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9
V
5.0
T
A
= 25C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
-1.7
V
5.0
T
A
= 25C (Note 5)
Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
PLH
Propagation Delay
1.0
6.4
ns
Figure 4
t
PHL
D
n
to O
n
1.5
6.7
t
PLH
Propagation Delay
1.0
7.1
ns
Figure 4
t
PHL
LE to O
n
1.5
7.5
t
PZH
Output Enable Time
0.8
6.5
ns
Figure 6
t
PZL
1.5
7.2
t
PHZ
Output Disable Time
1.5
7.7
ns
Figure 6
t
PLZ
Time
1.0
7.0
AC Operating Requirements
Symbol
Parameter
54ABT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
s
(H)
Set Time, HIGH
2.5
ns
Figure
7
t
s
(L)
or LOW D
n
to LE
2.5
t
h
(H)
Hold Time, HIGH
2.5
ns
Figure
7
t
h
(L)
or LOW D
n
to LE
2.5
t
w
(H)
Pulse Width,
3.3
ns
Figure
5
LE HIGH
Capacitance
Symbol
Parameter
Typ
Units
Conditions
(T
A
= 25C)
C
IN
Input Capacitance
5
pF
V
CC
= 0V
C
OUT
(Note 6)
Output Capacitance
9
pF
V
CC
= 5.0V
Note 6: C
OUT
is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
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4
Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
T
PLH
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to Output
DS100219-10
T
PHL
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to Output
DS100219-11
T
PZH
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, OE to Output
DS100219-12
T
PZL
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, OE to Output
DS100219-13
5
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Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
T
PHZ
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, OE to Output
DS100219-14
T
PLZ
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, OE to Output
DS100219-15
T
SET
LOW vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to LE
DS100219-16
T
SET
HIGH vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to LE
DS100219-17
T
HOLD
HIGH vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to LE
DS100219-18
T
HOLD
LOW vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, Data to LE
DS100219-19
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6
Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
T
PLH
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, Data to Output
DS100219-20
T
PHL
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, Data to Output
DS100219-21
T
PZH
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100219-22
T
PZL
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100219-23
T
PHZ
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100219-24
T
PLZ
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100219-25
7
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Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
T
PLH
vs Load Capacitance T
A
= 25C,
1 Output Switching, Data to Output
DS100219-26
T
PHL
vs Load Capacitance T
A
= 25C,
1 Output Switching, Data to Output
DS100219-27
T
PLH
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, Data to Output
DS100219-28
T
PHL
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, Data to Output
DS100219-29
T
PZH
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, OE to Output
DS100219-30
T
PZL
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, OE to Output
DS100219-31
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8
Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
T
PLH
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, LE to Output
DS100219-34
T
PHL
vs Temperature (T
A
), C
L
= 50 pF,
1 Output Switching, LE to Output
DS100219-35
T
PLH
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, LE to Output
DS100219-36
T
PHL
vs Temperature (T
A
), C
L
= 50 pF,
8 Outputs Switching, LE to Output
DS100219-37
T
PLH
and T
PHL
vs Number Outputs Switching,
C
L
= 50 pF, T
A
= 25C, V
CC
= 5.0V,
Outputs In Phase Data to Output
DS100219-32
Typical I
CC
vs Output Switching Frequency,
C
L
= 0 pF, V
CC
= V
IH
= 5.5V, LE = GND,
1 Output Switching at 50% Duty Cycle, Data to Output,
Transparent Mode with Unused Data Inputs = V
IH
DS100219-33
9
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AC Loading
DS100219-4
*Includes jig and probe capacitance
FIGURE 1. Test Load
DS100219-6
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100219-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100219-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100219-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100219-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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10
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier
NS Package Number E20A
20-Lead Ceramic Dual-In-Line
NS Package Number J20A
11
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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20-Lead Ceramic Flatpack
NS Package Number W20A
54ABT573
Octal
D-T
ype
Latch
with
TRI-ST
A
T
E
Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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