54ABT574
Octal D-Type Flip-Flop with TRI-STATE
Outputs
General Description
The 'ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE). The
information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the 'ABT374 except for
the pinouts.
Features
n
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
Functionally identical to 'ABT374
n
TRI-STATE outputs for bus-oriented applications
n
Output sink capability of 48 mA, source capability of
24 mA
n
Guaranteed multiple output switching specifications
n
Output switching specified for both 50 pF and 250 pF
loads
n
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n
Guaranteed latchup protection
n
High impedance glitch free bus loading during entire
power up and power down cycle
n
Non-destructive hot insertion capability
n
Standard Microcircuit Drawing (SMD) 5962-9322001
Ordering Code
Military
Package Number
Package Description
54ABT574J/883
J20A
20-Lead Ceramic Dual-In-Line
54ABT574W/883
W20A
20-Lead Cerpack
54ABT574E/883
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Descriptions
Pin
Description
Names
D
0
D
7
Data Inputs
CP
Clock Pulse Input
(Active Rising Edge)
OE
TRI-STATE Output Enable
Input (Active LOW)
O
0
O
7
TRI-STATE Outputs
FAST
and TRI-STATE
are registered trademarks of National Semiconductor Corporation.
Pin Assignment for DIP and Flatpak
DS100208-1
Pin Assignment
for LCC
DS100208-2
July 1998
54ABT574
Octal
D-T
ype
Flip-Flop
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100208
www.national.com
Functional Description
The 'ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold times require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs
Internal Outputs
Function
OE
CP
D
Q
O
H
H or L
L
NC
Z
Hold
Inputs
Internal Outputs
Function
OE
CP
D
Q
O
H
H or L
H
NC
Z
Hold
H
N
L
L
Z
Load
H
N
H
H
Z
Load
L
N
L
L
L
Data Available
L
N
H
H
H
Data Available
L
H or L
L
NC
NC
No Change in Data
L
H or L
H
NC
NC
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
DS100208-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output in
the Disabled or Power-Off State
-0.5V to 5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT574
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54ABT
2.5
V
Min
I
OH
= -3 mA
54ABT
2.0
V
Min
I
OH
= -24 mA
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Note 4)
5
V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
= 7.0V
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Note 4)
-5
V
IN
= 0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current
50
A
0 - 5.5V
V
OUT
= 2.7V; OE = 2.0V
I
OZL
Output Leakage Current
-50
A
0 - 5.5V
V
OUT
= 0.5V; OE = 2.0V
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0.0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
= V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
= 5.5V; All Other GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE = V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
2.5
mA
V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Max
Enable Input V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Data Input V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open, OE = GND,
(Note 4)
0.30
MHz
One Bit Toggling (Note 3),
50% Duty Cycle
Note 3: For 8-bit toggling, I
CCD
<
0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3
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AC Electrical Characteristics
54ABT
T
A
= -55C to +125C
Symbol
Parameter
V
CC
= 4.5V to 5.5V
Units
C
L
= 50 pF
Min
Max
f
max
Max Clock Frequency
150
MHz
t
PLH
Propagation Delay
1.5
7.0
ns
t
PHL
CP to O
n
1.5
7.4
t
PZH
Output Enable Time
1.0
6.5
ns
t
PZL
1.0
7.2
t
PHZ
Output Disable Time
1.0
7.2
ns
t
PLZ
1.0
6.7
AC Operating Requirements
54ABT
T
A
= -55C to +125C
Symbol
Parameter
V
CC
= 4.5V to 5.5V
Units
C
L
= 50 pF
Min
Max
t
s
(H)
Setup Time, HIGH
1.5
ns
t
s
(L)
or LOW D
n
to CP
2.0
t
h
(H)
Hold Time, HIGH
2.0
ns
t
h
(L)
or LOW D
n
to CP
2.0
t
w
(H)
Pulse Width, CP,
3.3
ns
t
w
(L)
HIGH or LOW
3.3
Capacitance
Symbol
Parameter
Typ
Units
Conditions
T
A
= 25C
C
IN
Input Capacitance
5.0
pF
V
CC
= 0V
C
OUT
(Note 5)
Output Capacitance
9.0
pF
V
CC
= 5.0V
Note 5: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
T
PHL
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Clock to Output
DS100208-12
T
PLH
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Clock to Output
DS100208-13
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4
Capacitance
(Continued)
T
PZH
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, OE to Output
DS100208-14
T
PZL
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, OE to Output
DS100208-15
T
PHZ
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, OE to Output
DS100208-16
T
PLZ
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, OE to Output
DS100208-17
T
SET
LOW vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Data to Clock
DS100208-18
T
SET
vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Data to Clock
DS100208-19
T
HOLD
HIGH vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Data to Clock
DS100208-20
T
HOLD
LOW vs Temperature (T
A
) C
L
= 50 pF,
1 Output Switching, Data to Clock
DS100208-21
5
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Capacitance
(Continued)
T
PLH
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, Clock to Output
DS100208-22
T
PHL
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, Clock to Output
DS100208-23
T
PZH
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100208-24
T
PZL
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100208-25
T
PHZ
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100208-26
T
PLZ
vs Temperature (T
A
) C
L
= 50 pF,
8 Outputs Switching, OE to Output
DS100208-27
T
PLH
vs Load Capacitance T
A
= 25C,
1 Output Switching, Clock to Output
DS100208-28
T
PHL
vs Load Capacitance T
A
= 25C,
1 Output Switching, Clock to Output
DS100208-29
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6
Capacitance
(Continued)
T
PLH
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, Clock to Output
DS100208-30
T
PHL
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, Clock to Output
DS100208-31
T
PZH
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, OE to Output
DS100208-32
T
PZL
vs Load Capacitance T
A
= 25C,
8 Outputs Switching, OE to Output
DS100208-33
T
PLH
and T
PHL
vs Number Outputs Switching
C
L
= 50 pF, T
A
= 25C, V
CC
= 5.0V,
Outputs In Phase, Clock to Output
DS100208-34
Typical I
CC
vs Output Switching Frequency
C
L
= 0 pF, V
CC
= V
IH
= 5.5V,
1 Output Switching at 50% Duty Cycle
DS100208-35
7
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AC Loading
DS100208-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100208-6
FIGURE 2. V
M
= 1.5V
Input Pulse Requirements
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100208-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100208-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100208-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100208-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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8
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
9
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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20-Lead Ceramic Flatpak (F)
NS Package Number W20A
54ABT574
Octal
D-T
ype
Flip-Flop
with
TRI-ST
A
T
E
Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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