54AC174/54ACT174
Hex D Flip-Flop with Master Reset
General Description
The 'AC/'ACT174 is a high-speed hex D flip-flop. The device
is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Features
n
I
CC
reduced by 50%
n
Outputs source/sink 24 mA
n
'ACT174 has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD)
-- 54AC174: 5962-87626
-- 54ACT174: 5962-87757
n
54AC174 now qualified to 300Krad RHA designation,
refer to the SMD for more information
Logic Symbols
10027701
IEEE/IEC
10027702
Pin Names
Description
D
0
D
5
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q
0
Q
5
Outputs
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
July 2003
54AC174/54ACT174
Hex
D
Flip-Flop
with
Master
Reset
2003 National Semiconductor Corporation
DS100277
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
10027703
10027704
Functional Description
The 'AC/'ACT174 consists of six edge-triggered D flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input's state is transferred to the corresponding flip-flop's
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The 'AC/'ACT174
is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Truth Table
Inputs
Output
MR
CP
D
Q
L
X
X
L
H
N
H
H
H
N
L
L
H
L
X
Q
H = HIGH Voltage Level
L = LOW Voltage Level
N
= LOW-to-HIGH Transition
X = Immaterial
Logic Diagram
10027705
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
54AC174/54ACT174
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+
0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'AC
2.0V to 6.0V
'ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54AC/ACT
-55C to +125C
Minimum Input Edge Rate (
V/t)
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (
V/t)
'ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
54AC
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
3.0
2.1
V
OUT
= 0.1V
Input Voltage
4.5
3.15
V
or V
CC
- 0.1V
5.5
3.85
V
IL
Maximum Low Level
3.0
0.9
V
OUT
= 0.1V
Input Voltage
4.5
1.35
V
or V
CC
- 0.1V
5.5
1.65
V
OH
Minimum High Level
3.0
2.9
I
OUT
= -50 A
Output Voltage
4.5
4.4
V
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
3.0
2.4
I
OH
= -12 mA
4.5
3.7
V
I
OH
= -24 mA
5.5
4.7
I
OH
= -24 mA
V
OL
Maximum Low Level
3.0
0.1
I
OUT
= 50 A
Output Voltage
4.5
0.1
V
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
3.0
0.50
I
OL
= 12 mA
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
54AC174/54ACT174
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3
DC Characteristics for 'AC Family Devices
(Continued)
54AC
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
I
OLD
Minimum Dynamic
Output Current (Note 3)
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
I
CC
for 54AC @ 25C is identical to 74AC @ 25C.
DC Characteristics for 'ACT Family Devices
54ACT
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 5)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 5)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
CCT
Maximum
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
Output Current (Note 6)
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: I
CC
for 54ACT @ 25C is identical to 74ACT @ 25C.
54AC174/54ACT174
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4
AC Electrical Characteristics
Symbol
Parameter
V
CC
54AC
Units
(V)
T
A
= -55C to +125C
Fig.
(Note 8)
C
L
= 50 pF
No.
Min
Max
f
max
Maximum Clock
3.3
65
MHz
Frequency
5.0
90
t
PLH
Propagation Delay
3.3
1.0
14.0
ns
CP to Q
n
5.0
1.5
10.5
t
PHL
Propagation Delay
3.3
1.0
13.0
ns
CP to Q
n
5.0
1.5
10.0
t
PHL
Propagation Delay
3.3
1.0
13.5
ns
MR to Q
n
5.0
1.5
11.0
Note 8: Voltage Range 3.3 is 3.3V
0.3V
Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
54AC
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 9)
C
L
= 50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
3.3
7.5
ns
D
n
to CP
5.0
5.5
t
h
Hold Time, HIGH or LOW
3.3
3.0
ns
D
n
to CP
5.0
3.0
t
w
MR Pulse Width, LOW
3.3
7.0
ns
5.0
5.0
t
w
CP Pulse Width
3.3
7.0
ns
5.0
5.0
t
rec
Recovery Time
3.3
3.0
ns
MR to CP
5.0
2.0
Note 9: Voltage Range 3.3 is 3.3V
0.3V
Voltage Range 5.0 is 5.0V
0.5V
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
(Note 10)
54ACT
Units
Fig.
No.
T
A
= -55C to +125C
C
L
= 50 pF
Min
Max
f
max
Maximum Clock
5.0
95
MHz
Frequency
t
PLH
Propagation Delay
5.0
1.5
12.5
ns
CP to Q
n
t
PHL
Propagation Delay
5.0
1.5
13.0
ns
CP to Q
n
t
PHL
Propagation Delay
5.0
1.5
12.0
ns
MR to Q
n
Note 10: Voltage Range 5.0 is 5.0V
0.5V
54AC174/54ACT174
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5
AC Operating Requirements
54ACT
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 11)
C
L
= 50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW
5.0
3.0
ns
D
n
to CP
t
h
Hold Time, HIGH or LOW
5.0
2.0
ns
D
n
to CP
t
w
MR Pulse Width, LOW
5.0
5.0
ns
t
w
CP Pulse Width, HIGH OR LOW
5.0
5.0
ns
t
rec
Recovery Time
5.0
1.0
ns
MR to CP
Note 11: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation
85.0
pF
V
CC
= 5.0V
Capacitance
54AC174/54ACT174
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6
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
54AC174/54ACT174
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7
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
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support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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54AC174/54ACT174
Hex
D
Flip-Flop
with
Master
Reset
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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