54ACT323
8-Bit Universal Shift/Storage Register with Synchronous
Reset and Common I/O Pins
General Description
The 'ACT323 is an 8-bit universal shift/storage register with
TRI-STATE
outputs. Parallel load inputs and flip-flop out-
puts are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q
0
and Q
7
to allow easy
cascading. Four operation modes are possible: hold (store),
shift left, shift right and parallel load.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Common parallel I/O for reduced pin count
n
Additional serial inputs and outputs for expansion
n
Four operating modes: shift left, shift right, load and
store
n
TRI-STATE outputs for bus-oriented applications
n
Outputs source/sink 24 mA
n
TTL-compatible inputs
n
Standard Military Drawing (SMD)
-- 'ACT323: 5962-91607
Logic Symbols
Pin Name
Description
CP
Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
SR
Synchronous Reset Input
OE
1
, OE
2
TRI-STATE Output Enable Inputs
I/O
0
I/O
7
Multiplexed Parallel Data Inputs or
TRI-STATE Parallel Data Outputs
Q
0
, Q
7
Serial Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100328-1
DS100328-5
July 1998
54ACT323
8-Bit
Universal
Shift/Storage
Register
with
Synchronous
Reset
and
Common
I/O
Pins
1998 National Semiconductor Corporation
DS100328
www.national.com
Connection Diagrams
Functional Description
The 'ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are
also brought out on other pins for expansion in serial shifting
of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, load, hold and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S
0
and S
1
in preparation for a parallel load
operation.
Mode Select Table
Inputs
Response
SR
S
1
S
0
CP
L
X
X
N
Synchronous Reset; Q
0
Q
7
= LOW
H
H
H
N
Parallel Load; I/O
n
Q
n
H
L
H
N
Shift Right; DS
0
Q
0
, Q
0
Q
1
, etc.
H
H
L
N
Shift Left; DS
7
Q
7
, Q
7
Q
6
, etc.
H
L
L
X
Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Clock Transition
Pin Assignment for
DIP and Flatpak
DS100328-2
Pin Assignment
for LCC
DS100328-3
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2
Logic Diagram
DS100328-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source or
Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACT
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics for 'ACT Family Devices
54ACT
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= -24 mA
5.5
0.50
I
OL
= -24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OZT
Maximum I/O
5.5
5.5
A
V
I/O
= V
CC
or GND
Leakage Current
V
IN
= V
IH
, V
IL
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
OLD
Minimum Dynamic Output
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Current (Note 3)
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
or GND
Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
CC
for 54ACT is identical to 74ACT
@
25C.
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4
AC Electrical Characteristics
54ACT
V
CC
T
A
= -55C
Symbol
Parameter
(V)
to +125C
Units
(Note 5)
C
L
= 50 pF
Min
Max
f
max
Maximum Input Frequency
5.0
70
MHz
t
PLH
Propagation Delay
5.0
1.0
16.5
ns
CP to Q
0
or Q
7
t
PHL
Propagation Delay
5.0
1.0
17.0
ns
CP to Q
0
or Q
7
t
PLH
Propagation Delay
5.0
1.0
16.5
ns
CP to I/O
n
t
PHL
Propagation Delay
5.0
1.0
18.0
ns
CP to I/O
n
t
PZH
Output Enable Time
5.0
1.0
15.5
ns
t
PZL
Output Enable Time
5.0
1.0
15.5
ns
t
PHZ
Output Disable Time
5.0
1.0
15.5
ns
t
PLZ
Output Disable Time
5.0
1.0
15.0
ns
Note 5: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
54ACT
T
A
= -55C
Symbol
Parameter
V
CC
to +125C
Units
(V)
C
L
= 50 pF
(Note 6)
V
CC
= +5.0V
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
6.0
ns
S
0
or S
1
to CP
t
h
Hold Time, HIGH or LOW
5.0
2.0
ns
S
0
or S
1
to CP
t
s
Setup Time, HIGH or LOW
5.0
4.5
ns
I/O
n
, DS
0
, DS
7
to CP
t
h
Hold Time, HIGH or LOW
5.0
2.0
ns
I/O
n
, DS
0
, DS
7
to CP
t
s
Setup Time, HIGH or LOW
5.0
3.0
ns
SR to CP
t
h
Hold Time, HIGH or LOW
5.0
1.5
ns
SR to CP
t
w
CP Pulse Width
5.0
5.0
ns
HIGH or LOW
Note 6: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation Capacitance
170
pF
V
CC
= 5.0V
5
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6
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fax: 81-3-5620-6179
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
54ACT323
8-Bit
Universal
Shift/Storage
Register
with
Synchronous
Reset
and
Common
I/O
Pins
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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