TL F 9548
54F74F533
Octal
Transparent
Latch
with
TRI-STATE
Outputs
May 1995
54F 74F533
Octal Transparent Latch with TRI-STATE
Outputs
General Description
The 'F533 consists of eight latches with TRI-STATE outputs
for bus organized system applications The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH
When LE is LOW the data that meets the setup times is
latched Data appears on the bus when the Output Enable
(OE) is LOW When OE is HIGH the bus output is in the high
impedance state The 'F533 is the same as the 'F373 ex-
cept that the outputs are inverted
Features
Y
Eight latches in a single package
Y
TRI-STATE outputs for bus interfacing
Y
Inverted version of the 'F373
Y
Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Package Description
Number
74F533PC
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
54F533DM (Note 2)
J20A
20-Lead Ceramic Dual-In-Line
74F533SC (Note 1)
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
74F533SJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
54F533FM (Note 2)
W20A
20-Lead Cerpack
54F533LM (Note 2)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
IEEE IEC
TL F 9548 4
TL F 9548 1
Pin Assignment
for DIP SOIC and Flatpak
TL F 9548 2
Pin Assignment
for LCC
TL F 9548 3
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
D
0
D
7
Data Inputs
1 0 1 0
20 mA
b
0 6 mA
LE
Latch Enable Input (Active HIGH)
1 0 1 0
20 mA
b
0 6 mA
OE
Output Enable Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
O
0
O
7
Complementary TRI-STATE Outputs
150 40 (33 3)
b
3 mA 24 mA (20 mA)
Function Table
Inputs
Output
LE
OE
D
O
H
L
H
L
H
L
L
H
L
L
X
O
0
X
H
X
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Functional Description
The 'F533 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the D
n
inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Logic Diagram
TL F 9548 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10% V
CC
2 5
I
OH
e b
1 mA
Voltage
54F 10% V
CC
2 4
I
OH
e b
3 mA
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA
74F 10% V
CC
2 4
I
OH
e b
3 mA
74F 5% V
CC
2 7
I
OH
e b
1 mA
74F 5% V
CC
2 7
I
OH
e b
3 mA
V
OL
Output LOW
54F 10% V
CC
0 5
V
Min
I
OL
e
20 mA
Voltage
74F 10% V
CC
0 5
I
OL
e
24 mA
I
IH
Input HIGH
54F
20 0
m
A
Max
V
IN
e
2 7V
Current
74F
5 0
I
BVI
Input HIGH Current
54F
100
m
A
Max
V
IN
e
7 0V
Breakdown Test
74F
7 0
I
BVIT
Input HIGH Current
54F
1 0
mA
Max
V
IN
e
5 5V
Breakdown (I O)
74F
0 5
I
CEX
Output HIGH
54F
250
m
A
Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4 75
V
0 0
I
ID
e
1 9 mA
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3 75
m
A
0 0
V
IOD
e
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V
I
OZH
Output Leakage Current
50
m
A
Max
V
OUT
e
2 7V
I
OZL
Output Leakage Current
b
50
m
A
Max
V
OUT
e
0 5V
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V
I
ZZ
Bus Drainage Test
500
m
A
0 0V
V
OUT
e
5 25V
I
CCZ
Power Supply Current
41
61
mA
Max
V
O
e
HIGH Z
3
AC Electrical Characteristics
74F
54F
74F
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Symbol
Parameter
V
CC
e a
5 0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
4 0
6 7
9 0
4 0
12 0
4 0
10 0
ns
t
PHL
D
n
to O
n
2 5
4 4
7 0
2 5
9 0
2 5
8 0
t
PLH
Propagation Delay
5 0
7 1
11 0
5 0
14 0
5 0
13 0
ns
t
PHL
LE to O
n
3 0
4 7
7 0
3 0
9 0
3 0
8 0
t
PZH
Output Enable Time
2 0
5 9
10 0
2 0
12 5
2 0
11 0
ns
t
PZL
2 0
5 6
7 5
2 0
10 5
2 0
8 5
t
PHZ
Output Disable Time
1 5
3 4
6 5
1 5
8 5
1 5
7 0
ns
t
PLZ
1 5
2 7
5 5
1 5
7 5
1 5
6 5
AC Operating Requirements
74F
54F
74F
Symbol
Parameter
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Units
V
CC
e a
5 0V
Min
Max
Min
Max
Min
Max
t
s
(H)
Setup Time HIGH or LOW
2 0
2 0
2 0
ns
t
s
(L)
D
n
to LE
2 0
2 0
2 0
t
h
(H)
Hold Time HIGH or LOW
3 0
3 0
3 0
ns
t
h
(L)
D
n
to LE
3 0
3 0
3 0
t
w
(H)
LE Pulse Width HIGH
6 0
6 0
6 0
ns
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows
74F
533
S
C
X
Temperature Range Family
Special Variations
74F
e
Commercial
X
e
Devices shipped in 13 reels
54F
e
Military
QB
e
Military grade device with
environmental and burn-in
Device Type
processing shipped in tubes
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0 C to
a
70 C)
D
e
Ceramic DIP
M
e
Military (
b
55 C to
a
125 C)
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
4
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
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