54FCT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The 'FCT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n
Clock enable for address and data synchronization
applications
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
See 'FCT273 for master reset version
n
See 'FCT373 for transparent latch version
n
See 'FCT374 for TRI-STATE
version
n
TTL input and output level compatible
n
CMOS power consumption
n
Output sink capability of 32 mA, source capability of
12 mA
n
Standard Microcircuit Drawing (SMD) 5962-8762701
Ordering Code
Military
Package
Package Description
Number
54FCT377DMQB
J20A
20-Lead Ceramic Dual-In-Line
54FCT377FMQB
W20A
20-Lead Cerpack
54FCT377LMQB
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names
Description
D
0
D
7
Data Inputs
CE
Clock Enable (Active LOW)
CP
Clock Pulse Input
Q
0
Q
7
Data Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Pin Assignment for
DIP and Cerpack
DS100952-1
Pin Assignment for LCC
DS100952-11
October 1999
54FCT377
Octal
D-T
ype
Flip-Flop
with
Clock
Enable
1999 National Semiconductor Corporation
DS100952
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Truth Table
Mode Select-Function Table
Operating Mode
Inputs
Output
CP
CE
D
n
Q
n
Load "1"
I
h
H
Load "0"
I
I
L
Hold
h
X
No Change
(Do Nothing)
X
H
X
No Change
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
DS100952-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
54FCT377
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-0.5V to +4.75V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
Twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
(Across Comm Operating Range)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
DC Electrical Characteristics
Symbol
Parameter
FCT377
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54FCT
4.3
V
Min
I
OH
= -300 uA
54FCT
2.4
I
OH
= -12 mA
V
OL
Output LOW Voltage
54FCT
0.2
V
Min
I
OL
= 300 uA
54FCT
0.5
I
OL
= 32mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= V
CC
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V
I
OS
Output Short-Circuit Current
-60
mA
Max
V
OUT
= 0.0V
I
CCQ
Quiescent Power
Supply Current
1.5
mA
Max
V
I
= 0.2V or V
I
= 5.3V, V
CC
= 5.5V
I
CC
Maximum I
CC
/Input
V
I
= V
CC
- 2.1V
2.0
mA
Max
Data Input V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
0.4
mA/
Max
Outputs Open
MHz
One bit Toggling, 50% Duty Cycle
I
CC
Total Power Supply
Current
6.0
mA
Max
V
CC
= 5.5V, Outputs Open, f
CP
=
10MHz, 50% Duty Cycle, One bit
Toggling at f
I
= 5 MHz, 50% Duty
Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
54FCT377
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3
AC Electrical Characteristics
Symbol
Parameter
54FCT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
PLH
Propagation Delay
2.0
15.0
ns
Figure 4
t
PHL
CP to O
n
2.0
8.3
AC Operating Requirements
54FCT
T
A
= -55C to +125C
Fig.
Symbol
Parameter
V
CC
= 4.5V to 5.5V
Units
No.
C
L
= 50 pF
Min
Max
t
s
(H)
Setup Time, HIGH
4.0
ns
Figure 6
t
s
(L)
or LOW D
n
to CP
4.0
t
h
(H)
Hold Time, HIGH
2.5
ns
Figure 6
t
h
(L)
or LOW D
n
to CP
2.5
t
s
(H)
Setup Time, HIGH
4.5
ns
Figure 6
t
s
(L)
or LOW CE to CP
4.5
t
h
(H)
Hold Time, HIGH
2.0
ns
Figure 6
t
h
(L)
or LOW CE to CP
2.0
t
w
(H)
Pulse Width, CP,
7.0
ns
Figure 5
t
w
(L)
HIGH or LOW
7.0
Capacitance
Symbol
Parameter
Max
Units
Conditions
C
IN
Input Capacitance
10
pF
V
CC
= 0V, T
A
= 25C
C
OUT
(Note 3)
Output Capacitance
12
pF
V
CC
= 5.0V
Note 3: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
54FCT377
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4
AC Loading
Input Pulse Requirements
DS100952-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100952-6
FIGURE 2. V
M
= 1.5V
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100952-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100952-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100952-9
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
54FCT377
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5
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Ceramic Chip Carrier
NS Package Number E20A
54FCT377
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package
NS Package Number J20A
20-Lead Ceramic Flatpack
NS Package Number W20A
54FCT377
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7
Notes
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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www.national.com
54FCT377
Octal
D-T
ype
Flip-Flop
with
Clock
Enable
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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