54FCT533
Octal Transparent Latch with TRI-STATE
Outputs
General Description
The FCT533 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing re-
quirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus out-
put is in the high impedance state.
Features
n
Eight latches in a single package
n
TTL input and output level compatible
n
CMOS power consumption
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Output sink capability of 32mA, source capability of 12
mA
n
Inverted version of the FCT373
n
Standard Microcircuit Drawing (SMD) 5962-8865101
Logic Symbols
Pin
Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O
0
O
7
TRI-STATE Latch
Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100969-1
IEEE/IEC
DS100969-2
September 1998
54FCT533
Octal
T
ransparent
Latch
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100969
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Connection Diagrams
Functional Description
The FCT533 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
Outputs
LE
OE
D
n
O
n
X
H
X
Z
H
L
L
H
H
L
H
L
L
L
X
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100969-3
Pin Assignment
for LCC
DS100969-4
DS100969-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latchup Source
or Sink Current
300 mA
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'FCT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54FCT
-55C to +125C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
circuits outside databook specifications.
DC Characteristics for 'FCT Family Devices
Symbol
Parameter
FCT541
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54FCT
4.3
V
Min
I
OH
= -300 A
54FCT
2.4
V
Min
I
OH
= -12 mA
V
OL
Output LOW Voltage
54FCT
0.2
V
Min
I
OL
= 300 A
54FCT
0.5
V
Min
I
OL
= 32 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= V
CC
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.0V
I
OZH
Output Leakage Current
10
A
Max
V
OUT
= 5.5V; OE
n
= 2.0V
I
OZL
Output Leakage Current
-10
A
Max
V
OUT
= 0.0V; OE
n
= 2.0V
I
OS
Output Short-Circuit Current
-60
mA
Max
V
OUT
= 0.0V
I
CCQ
Quiescent Power
Supply Current
1.5
mA
Max
V
IN
<
0.2V or V
IN
5.3V, V
CC
=
5.5V
I
CC
Quiescent Power
Supply Current
2.0
mA
Max
V
I
= V
CC
- 2.1V
I
CCD
Dynamic I
CC
0.4
mA/
MHz
Max
V
CC
= 5.5V, Outputs Open,
One Bit Toggling, 50% Duty
Cycle, OE
n
= GND
I
CC
Total Power Supply
Current
6.0
mA
Max
V
CC
= 5.5V, Outputs Open, fI
= 10MHz, OE
n
= GND, One
Bit Toggling, 50% Duty Cycle
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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AC Electrical Characteristics
54FCT
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 4)
C
L
= 50 pF
Min
Max
t
PHL
, t
PLH
Propagation Delay
5.0
1.5
12.0
ns
D
n
to O
n
t
PHL
, t
PLH
Propagation Delay
5.0
2.0
14.0
ns
LE to O
n
t
PZL
, t
PZH
Output Enable Time
5.0
1.5
12.5
ns
t
PHZ
, t
PLZ
Output Disable Time
5.0
1.5
8.5
ns
Note 4: Voltage Range 5.0 is 5.0V
0.5V.
AC Operating Requirements
54FCT
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 5)
C
L
= 50 pF
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
2.0
ns
D
n
to LE
t
H
Hold Time, HIGH or LOW
5.0
3.0
ns
D
n
to LE
t
W
LE Pulse Width, HIGH
5.0
6.0
ns
Note 5: Voltage Range 5.0 is 5.0V
0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
10
pF
V
CC
= OPEN
C
PD
Power Dissipation
40
pF
V
CC
= 5.0V
Capacitance
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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