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Электронный компонент: 54FCT573LMQB

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54FCT573
Octal D-Type Latch with TRI-STATE
Outputs
General Description
The 'FCT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE) in-
puts.
This device is functionally identical to the 'FCT373 but has
different pinouts.
Features
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
TTL input and output level compatible
n
CMOS power consumption
n
Functionally identical to 'FCT373
n
TRI-STATE outputs for bus interfacing
n
Output sink capability of 32 mA, source capability of
12 mA
n
Standard Microcircuit Drawing (SMD) 5962-8863901
Ordering Code
Military
Package
Package Description
Number
54FCT573DMQB
J20A
20-Lead Ceramic Dual-In-Line
54FCT573FMQB
W20A
20-Lead Cerpack
54FCT573LMQB
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
TRI-STATE Output Enable Input
(Active LOW)
O
0
O
7
TRI-STATE Latch Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Pin Assignment
for DIP and Cerpack
DS100951-1
Pin Assignment
for LCC
DS100951-39
August 1998
54FCT573
Octal
D-T
ype
Latch
with
TRI-ST
A
T
E
Outputs
1999 National Semiconductor Corporation
DS100951
www.national.com
Functional Description
The 'FCT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Function Table
Inputs
Outputs
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
O
0
H
X
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O
0
= Value stored from previous clock cycle
Logic Diagram
DS100951-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
54FCT573
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-0.5V to +5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
Twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
FCT573
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH
Voltage
54FCT
4.3
V
Min
I
OH
= -300 A
54FCT
2.4
I
OH
= -12 mA
V
OL
Output LOW
Voltage
54FCT
0.2
V
Min
I
OL
= 300 A
54FCT
0.5
I
OL
= 32 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= V
CC
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.0V
I
OZH
Output Leakage Current
50
A
0 -
5.5V
V
OUT
= 2.7V; OE = 2.0V
I
OZL
Output Leakage Current
-50
A
0 -
5.5V
V
OUT
= 0.5V; OE = 2.0V
I
OS
Output Short-Circuit Current
-60
mA
Max
V
OUT
= 0.0V
I
CCQ
Quiescent Power Supply Current
1.5
mA
Max
V
IN
<
0.2V or V
IN
5.3V, V
CC
=
5.5V
I
CC
Quiescent Power
Supply Current
2.0
mA
Max
V
I
= 3.4V, V
CC
= 5.5V
I
CCD
Dynamic I
CC
0.4
mA/
MHz
Max
Outputs Open, V
CC
= 5.5V, V
IN
5.3V or V
IN
<
0.2V, One Bit
Toggling, 50% Duty Cycle, OE =
GND, LE = V
CC
I
CC
Total Power Supply
Current
6.0
mA
Max
Outputs Open, f
CP
= 10 MHz,
V
CC
= 5.5V, V
IN
5.3V or V
IN
<
0.2V, One Bit Toggling, 50%
Duty Cycle, OE = GND, LE =
V
CC
54FCT573
www.national.com
3
AC Electrical Characteristics
Symbol
Parameter
54FCT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
PLH
Propagation Delay
1.0
8.5
ns
Figure 4
t
PHL
D
n
to O
n
1.0
8.5
t
PLH
Propagation Delay
1.0
15.0
ns
Figure 4
t
PHL
LE to O
n
1.0
15.0
t
PZH
Output Enable Time
1.0
13.5
ns
Figure 6
t
PZL
1.0
13.5
t
PHZ
Output Disable Time
1.0
10.0
ns
Figure 6
t
PLZ
Time
1.0
10.0
AC Operating Requirements
Symbol
Parameter
54FCT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
s
(H)
Set Time, HIGH
2.0
ns
Figure 7
t
s
(L)
or LOW D
n
to LE
2.0
t
h
(H)
Hold Time, HIGH
1.5
ns
Figure 7
t
h
(L)
or LOW D
n
to LE
1.5
t
w
(H)
Pulse Width,
6.0
ns
Figure 5
LE HIGH
Capacitance
Symbol
Parameter
Max
Units
Conditions
(T
A
= 25C)
C
IN
Input Capacitance
10
pF
V
CC
= 0V
C
OUT
(Note 3)
Output Capacitance
12
pF
V
CC
= 5.0V
Note 3: C
OUT
is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
54FCT573
www.national.com
4
AC Loading
DS100951-4
*Includes jig and probe capacitance
FIGURE 1. Test Load
DS100951-6
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100951-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100951-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100951-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100951-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
54FCT573
www.national.com
5