54LCX16374
Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs
and Outputs
General Description
The LCX16374 contains sixteen non-inverting D flip-flops
with TRI-STATE
outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The LCX16374 is designed for low voltage (3.3V) V
CC
appli-
cations with capability of interfacing to a 5V signal environ-
ment.
The LCX16374 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
n
5V tolerant inputs and outputs
n
Power down high impedance inputs and outputs
n
Supports live insertion/withdrawal
n
2.0V3.6V V
CC
supply operation
n
24 mA output drive
n
Implements patented noise/EMI reduction circuitry
n
Functionally compatible with the 54 series 16374
n
ESD performance:
Human body model
>
2000V
Machine model
>
200V
n
Standard Microcircuit Drawing (SMD) 5962-99535
Ordering Code
Order Number
Package Number
Package Description
54LCX16374W-QML
WA48A
48-Lead Ceramic Flatpack
Logic Symbol
Pin Descriptions
Pin
Description
Names
OE
n
Output Enable Input (Active Low)
CP
n
Clock Pulse Input
I
0
I
15
Inputs
O
0
O
15
Outputs
Connection Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS101199-1
Pin Assignment for
Cerpack
DS101199-2
July 1999
54LCX16374
Low
V
oltage
16-Bit
D
Flip-Flop
with
5V
T
olerant
Inputs
and
Outputs
1999 National Semiconductor Corporation
DS101199
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Functional Description
The LCX16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs andTRI-STATE true outputs.
The device is byte controlled with each byte functioning iden-
tically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. Each byte
has a buffered clock and buffered Output Enable common to
all flip-flops within that byte. The description which follows
applies to each byte. Each flip-flop will store the state of their
individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP
n
) transition. With the
Output Enable (OE
n
) LOW, the contents of the flip-flops are
available at the outputs. When OE
n
is HIGH, the outputs go
to the high impedance state. Operation of the OE
n
input
does not affect the state of the flip-flops.
Inputs
Outputs
CP
1
OE
1
I
0
I
7
O
0
O
7
L
H
H
L
L
L
L
L
X
O
0
X
H
X
Z
Inputs
Outputs
CP
2
OE
2
I
8
I
15
O
8
O
15
L
H
H
L
L
L
L
L
X
O
0
X
H
X
Z
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
O
0
= Previous O
0
before HIGH to LOW of CP
Logic Diagrams
Byte 1 (0:7)
DS101199-3
Byte 2 (8:15)
DS101199-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Voltage (V
I
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
<
GND
-50 mA
DC Output Diode Current (I
OK
)
V
O
<
GND
-50mA
V
O
V
CC
+50mA
DC Output Voltage (V
O
) (Note
2)
Output in High or Low State
-0.5V to V
CC
+ 0.5V
Output in TRI-STATE
-0.5V to 7.0V
DC Output Source or Sink
Current (I
O
)
50mA
DC V
CC
or Ground Current
100mA
Storage Temperature Range
(T
STG
)
-65C to +150C
Power Dissapation
750mW
Junction Temperature (T
J
)
175C
Recommended Operating
Conditions
(Note 3)
Supply Voltage (V
CC
)
Operating
2.0V to 3.6V
Data Retention
1.5V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
High or Low State
0V to V
CC
TRI-STATE
0V to 5.5V
Operating Temperature (T
A
)
-55C to
+125C
Minimum Input Edge Rate (
t/
V)
V
IN
from 0.8V to 2.0V, V
CC
= 3.0V
0ns/V to 10ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the Absolute Maximum Ratings. The
"Recommended Operating Conditions" table will define the conditions for ac-
tual device operation.
Note 2: I
O
Absolute Maximum Rating must be observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Conditions
V
CC
T
A
= -55C to +125C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.73.6
2.0
V
V
IL
LOW Level Input Voltage
2.73.6
0.8
V
V
OH
HIGH Level Output Voltage
I
OH
= -100 A
2.73.6
V
CC
- 0.2
V
I
OH
= -12 mA
2.7
2.2
V
I
OH
= -12 mA
3.0
2.4
V
I
OH
= -24 mA
3.0
2.2
V
V
OL
LOW Level Output Voltage
I
OL
= 100 A
2.73.6
0.2
V
I
OL
= 12 mA
2.7
0.4
V
I
OL
= 24 mA
3.0
0.55
V
I
I
Input Leakage Current
0
V
I
5.5V
2.73.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
5.5V
2.73.6
5.0
A
V
I
= V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
= 5.5V
0
10
A
I
CC
Quiescent Supply Current
V
I
= V
CC
or GND
2.73.6
20
A
3.6V
V
I
, V
O
5.5V
2.73.6
20
A
I
CC
Increase in I
CC
per Input
V
IH
= V
CC
-0.6V
2.73.6
500
A
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3
AC Electrical Characteristics
Symbol
Parameter
T
A
= -55C to +125C, C
L
= 50pF, R
L
= 500
Units
V
CC
= 3.3V
0.3V
V
CC
= 2.7V
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
200
200
MHz
t
PHL
Propagation Delay
0.5
6.5
1.0
7.0
ns
t
PLH
CP to O
n
0.5
6.5
1.0
7.0
t
PZL
Output Enable Time
0.5
6.5
1.0
7.0
ns
t
PZH
0.5
6.5
1.0
7.0
t
PLZ
Output Disable Time
1.0
6.5
1.0
7.0
ns
t
PHZ
1.0
6.5
1.0
7.0
t
S
Setup Time
3.5
3.5
ns
t
H
Hold Time
2.0
2.0
ns
t
W
Pulse Width
4.0
4.0
ns
t
OSHL
Output to Output Skew (Note 4)
1.0
1.0
ns
t
OSLH
1.0
1.0
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two seperate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
Parameter
Conditions
V
CC
(V)
T
A
= 25C
Units
Max
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
= 50 pF, V
IH
= 3.3V, V
IL
= 0V
3.3
1.2
V
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
= 50 pF, V
IH
= 3.3V, V
IL
= 0V
3.3
-1.1
V
Capacitance
Symbol
Parameter
Conditions
Max
Units
C
IN
Input Capacitance
V
CC
= Open, V
I
= 0V or V
CC
10
pF
C
OUT
Output Capacitance
V
CC
= 3.3V, V
I
= 0V or V
CC
12
pF
C
PD
Power Dissipation Capacitance
V
CC
= 3.3V, V
I
= 0V or V
CC
, f = 10 MHz
40
pF
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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www.national.com
48-Lead Ceramic Flatpack
Package Number WA48A
54LCX16374
Low
V
oltage
16-Bit
D
Flip-Flop
with
5V
T
olerant
Inputs
and
Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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