TL F 6397
54LS161ADM54LS161ADM74LS161A
54LS163ADM54LS163ADM74LS163A
Synchronous
4-Bit
Binary
Counters
May 1992
54LS161A DM54LS161A DM74LS161A
54LS163A DM54LS163A DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs The LS161A and LS163A are 4-bit binary counters
The carry output is decoded by means of a NOR gate thus
preventing spikes during the normal counting mode of oper-
ation Synchronous operation is provided by having all flip-
flops clocked simultaneously so that the outputs change co-
incident with each other when so instructed by the count-
enable inputs and internal gating This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform
These counters are fully programmable that is the outputs
may be preset to either level As presetting is synchronous
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input The clear function for the LS161A is asynchronous
and a low level at the clear input sets all four of the flip-flop
outputs low regardless of the levels of clock load or en-
able inputs The clear function for the LS163A is synchro-
nous and a low level at the clear inputs sets all four of the
flip-flop outputs low after the next clock pulse regardless of
the levels of the enable inputs This synchronous clear al-
lows the count length to be modified easily as decoding the
maximum count desired can be accomplished with one ex-
ternal NAND gate The gate output is connected to the clear
input to synchronously clear the counter to all low outputs
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output
Both count-enable inputs (P and T) must be high to count
and input T is fed forward to enable the ripple carry output
The ripple carry output thus enabled will produce a high-lev-
el output pulse with a duration approximately equal to the
high-level portion of the Q
A
output This high-level overflow
ripple carry pulse can be used to enable successive cascad-
ed stages High-to-low level transitions at the enable P or T
inputs may occur regardless of the logic level of the clock
These counters feature a fully independent clock circuit
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs The function of the counter (whether enabled dis-
abled loading or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times
Features
Y
Synchronously programmable
Y
Internal look-ahead for fast counting
Y
Carry output for n-bit cascading
Y
Synchronous counting
Y
Load control line
Y
Diode-clamped inputs
Y
Typical propagation time clock to Q output 14 ns
Y
Typical clock frequency 32 MHz
Y
Typical power dissipation 93 mW
Y
Alternate
Military Aerospace
device
(54LS161
54LS163) is available Contact a National Semiconduc-
tor Sales Office Distributor for specificaitons
Connection Diagram
Dual-In-Line Package
TL F 6397 1
Order Numbers 54LS161ADMQB 54LS161AFMQB
54LS161ALMQB 54LS163ADMQB 54LS163AFMQB
54LS163ALMQB DM54LS161AJ DM54LS161AW
DM54LS163AJ DM54LS163AW DM74LS161AM
DM74LS161AN DM74LS163AM or DM74LS163AN
See NS Package Number E20A J16A
M16A N16E or W16A
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
b
55 C to
a
125 C
DM74LS
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54LS161A
DM74LS161A
Units
Min
Nom
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 7
0 8
V
I
OH
High Level Output Current
b
0 4
b
0 4
mA
I
OL
Low Level Output Current
4
8
mA
f
CLK
Clock Frequency (Note 1)
0
25
0
25
MHz
Clock Frequency (Note 2)
0
20
0
20
MHz
t
W
Pulse Width
Clock
20
6
20
6
ns
(Note 1)
Clear
20
9
20
9
Pulse Width
Clock
25
25
ns
(Note 2)
Clear
25
25
t
SU
Setup Time
Data
20
8
20
8
(Note 1)
Enable P
25
17
25
17
ns
Load
25
15
25
15
Setup Time
Data
20
20
(Note 2)
Enable P
30
30
ns
Load
30
30
t
H
Hold Time
Data
0
b
3
0
b
3
ns
(Note 1)
Others
0
b
3
0
b
3
Hold Time
Data
5
5
ns
(Note 2)
Others
5
5
t
REL
Clear Release Time (Note 1)
20
20
ns
Clear Release Time (Note 2)
25
25
ns
T
A
Free Air Operating Temperature
b
55
125
0
70
C
Note 1
C
L
e
15 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5 5V
Note 2
C
L
e
50 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5 5V
2
'LS161 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
18 mA
b
1 5
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
DM54
2 5
3 4
V
Voltage
V
IL
e
Max V
IH
e
Min
DM74
2 7
3 4
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
DM54
0 25
0 4
Voltage
V
IL
e
Max V
IH
e
Min
DM74
0 35
0 5
V
I
OL
e
4 mA V
CC
e
Min
DM74
0 25
0 4
I
I
Input Current
Max
V
CC
e
Max
Enable T
0 2
Input Voltage
V
I
e
7V
Clock
0 2
mA
Load
0 2
Others
0 1
I
IH
High Level Input
V
CC
e
Max
Enable T
40
Current
V
I
e
2 7V
Clock
40
m
A
Load
40
Others
20
I
IL
Low Level Input
V
CC
e
Max
Enable T
b
0 8
Current
V
I
e
0 4V
Clock
b
0 8
mA
Load
b
0 8
Others
b
0 4
I
OS
Short Circuit
V
CC
e
Max
DM54
b
20
b
100
mA
Output Current
(Note 2)
DM74
b
20
b
100
I
CCH
Supply Current with
V
CC
e
Max
18
31
mA
Outputs High
(Note 3)
I
CCL
Supply Current with
V
CC
e
Max
19
32
mA
Outputs Low
(Note 4)
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CCH
is measured with the load high then again with the load low with all other inputs high and all outputs open
Note 4
I
CCL
is measured with the clock input high then again with the clock input low with all other inputs low and all outputs open
'LS161 Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
From (Input)
R
L
e
2 kX
Symbol
Parameter
To (Output)
C
L
e
15 pF
C
L
e
50 pF
Units
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
25
20
MHz
t
PLH
Propagation Delay Time
Clock to
25
30
ns
Low to High Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Clock to
30
38
ns
High to Low Level Output
Ripple Carry
t
PLH
Propagation Delay Time
Clock to Any Q
22
27
ns
Low to High Level Output
(Load High)
t
PHL
Propagation Delay Time
Clock to Any Q
27
38
ns
High to Low Level Output
(Load High)
3
'LS161 Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load) (Continued)
From (Input)
R
L
e
2 kX
Symbol
Parameter
To (Output)
C
L
e
15 pF
C
L
e
50 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time
Clock to Any Q
24
30
ns
Low to High Level Output
(Load Low)
t
PHL
Propagation Delay Time
Clock to Any Q
27
38
ns
High to Low Level Output
(Load Low)
t
PLH
Propagation Delay Time
Enable T to
14
27
ns
Low to High Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Enable T to
15
27
ns
High to Low Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Clear to
28
45
ns
High to Low Level Output
Any Q
Recommended Operating Conditions
Symbol
Parameter
DM54LS163A
DM74LS163A
Units
Min
Nom
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 7
0 8
V
I
OH
High Level Output Current
b
0 4
b
0 4
mA
I
OL
Low Level Output Current
4
8
mA
f
CLK
Clock Frequency (Note 1)
0
25
0
25
MHz
Clock Frequency (Note 2)
0
20
0
20
MHz
t
W
Pulse Width
Clock
20
6
20
6
ns
(Note 1)
Clear
20
9
20
9
Pulse Width
Clock
25
25
ns
(Note 2)
Clear
25
25
t
SU
Setup Time
Data
20
8
20
8
(Note 1)
Enable P
25
17
25
17
ns
Load
25
15
25
15
Setup Time
Data
20
20
(Note 2)
Enable P
30
30
ns
Load
30
30
t
H
Hold Time
Data
0
b
3
0
b
3
ns
(Note 1)
Others
0
b
3
0
b
3
Hold Time
Data
5
5
ns
(Note 2)
Others
5
5
t
REL
Clear Release Time (Note 1)
20
20
ns
Clear Release Time (Note 2)
25
25
ns
T
A
Free Air Operating Temperature
b
55
125
0
70
C
Note 1
C
L
e
15 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5V
Note 2
C
L
e
50 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5V
4
'LS163 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
18 mA
b
1 5
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
DM54
2 5
3 4
V
Voltage
V
IL
e
Max V
IH
e
Min
DM74
2 7
3 4
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
DM54
0 25
0 4
Voltage
V
IL
e
Max V
IH
e
Min
DM74
0 35
0 5
V
I
OL
e
4 mA V
CC
e
Min
DM74
0 25
0 4
I
I
Input Current
Max
V
CC
e
Max
Enable T
0 2
Input Voltage
V
I
e
7V
Clock Clear
0 2
mA
Load
0 2
Others
0 1
I
IH
High Level Input
V
CC
e
Max
Enable T
40
Current
V
I
e
2 7V
Load
40
m
A
Clock Clear
40
Others
20
I
IL
Low Level Input
V
CC
e
Max
Enable T
b
0 8
Current
V
I
e
0 4V
Clock Clear
b
0 8
mA
Load
b
0 8
Others
b
0 4
I
OS
Short Circuit
V
CC
e
Max
DM54
b
20
b
100
mA
Output Current
(Note 2)
DM74
b
20
b
100
I
CCH
Supply Current with
V
CC
e
Max
18
31
mA
Outputs High
(Note 3)
I
CCL
Supply Current with
V
CC
e
Max
18
32
mA
Outputs Low
(Note 4)
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CCH
is measured with the load high then again with the load low with all other inputs high and all outputs open
Note 4
I
CCL
is measured with the clock input high then again with the clock input low with all other inputs low and all outputs open
'LS163 Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
From (Input)
R
L
e
2 kX
Symbol
Parameter
To (Output)
C
L
e
15 pF
C
L
e
50 pF
Units
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
25
20
MHz
t
PLH
Propagation Delay Time
Clock to
25
30
ns
Low to High Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Clock to
30
38
ns
High to Low Level Output
Ripple Carry
t
PLH
Propagation Delay Time
Clock to Any Q
22
27
ns
Low to High Level Output
(Load High)
t
PHL
Propagation Delay Time
Clock to Any Q
27
38
ns
High to Low Level Output
(Load High)
5
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