TL F 10178
54LS192DM74LS192
UpDown
Decade
Counter
with
Separate
UpDown
Clocks
May 1992
54LS192 DM74LS192 Up Down Decade Counter
with Separate Up Down Clocks
General Description
The 'LS192 is an up down BCD decade (8421) counter
Separate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously
The outputs change state synchronous with the LOW-to-
HIGH transitions on the clock inputs
Separate Terminal Count Up and Terminal Count Down out-
puts are provided which are used as the clocks for a subse-
quent stage without extra logic thus simplifying multistage
counter designs Individual preset inputs allow the circuits to
be used as programmable counters Both the Parallel Load
(PL) and the Master Reset (MR) inputs asynchronously
override the clocks
Connection Diagram
Dual-In-Line Package
TL F 10178 1
Order Number 54LS192DMQB 54LS192FMQB
54LS192LMQB DM74LS192M or DM74LS192N
See NS Package Number E20A J16A
M16A N16E or W16A
Logic Symbol
TL F 10178 2
V
CC
e
Pin 16
GND
e
Pin 8
Pin Names
Description
CP
U
Count Up Clock Input
(Active Rising Edge)
CP
D
Count Down Clock Input
(Active Rising Edge)
MR
Asynchronous Master Reset Input
(Active HIGH)
PL
Asynchronous Parallel Load Input
(Active LOW)
P0 P3
Parallel Data Inputs
Q0 Q3
Flip-Flop Outputs
TC
D
Terminal Count Down (Borrow)
Output (Active LOW)
TC
U
Terminal Count Up (Carry)
Output (Active LOW)
Mode Select Table
MR
PL
CP
U
CP
D
Mode
H
X
X
X
Reset (Asyn )
L
L
X
X
Preset (Asyn )
L
H
H
H
No Change
L
H
L
H
Count Up
L
H
H
L
Count Down
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
b
55 C to
a
125 C
DM74LS
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
54LS192
DM74LS192
Units
Min
Nom
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 7
0 8
V
I
OH
High Level Output Voltage
b
0 4
b
0 4
mA
I
OL
Low Level Output Current
4
8
mA
T
A
Free Air Operating Temperature
b
55
125
0
70
C
t
s
(H)
Setup Time HIGH or LOW
20
20
ns
t
s
(L)
Pn to PL
20
10
t
h
(H)
Hold Time HIGH or LOW
3
3
ns
t
h
(L)
Pn to PL
3
3
t
w
(L)
CP Pulse Width LOW
17
17
ns
t
w
(L)
PL Pulse Width LOW
20
20
ns
t
w
(H)
MR Pulse Width HIGH
15
15
ns
t
rec
Recovery Time MR to CP
3
3
ns
t
rec
Recovery Time PL to CP
10
10
ns
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
18 mA
b
1 5
V
V
OH
High Level Output Voltage
V
CC
e
Min I
OH
e
Max
54LS
2 5
V
V
IL
e
Max
DM74
2 7
V
OL
Low Level Output Voltage
V
CC
e
Min I
OL
e
Max
54LS
0 4
V
IH
e
Min
DM74
0 5
V
I
OL
e
4 mA V
CC
e
Min
DM74
0 4
I
I
Input Current
Max
V
CC
e
Max V
I
e
10V
DM54
0 1
mA
Input Voltage
V
I
e
7V
DM74
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 7V
20
m
A
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 4V
b
0 4
mA
I
OS
Short Circuit
V
CC
e
Max
54LS
b
20
b
100
mA
Output Current
(Note 2)
DM74
b
20
b
100
I
CC
Supply Current
V
CC
e
Max MR PL
e
GND
31
mA
Other Inputs
e
4 5V
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
2
Switching Characterisitcs
V
CC
e a
0 5V T
A
e a
25 C (See Section 1 for waveforms and load configurations)
R
L
e
2k
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
f
max
Maximum Count Frequency
30
MHz
t
PLH
Propagation Delay
31
ns
t
PHL
CP
U
or CP
D
to Q
n
28
t
PLH
Propagation Delay
16
t
PHL
CP
U
to TC
U
21
ns
t
PLH
Propagation Delay
16
t
PHL
CP
D
to TC
D
24
t
PLH
Propagation Delay
20
ns
t
PHL
P
n
to Q
n
30
t
PLH
Propagation Delay
32
t
PHL
PL to Q
n
30
ns
t
PHL
Propagation Delay MR to Q
n
25
Functional Description
The '192 is an asynchronously presettable decade and 4-bit
binary synchronous up down (reversible) counter The op-
erating modes of the '192 decade counter and the '193 bi-
nary counter are identical with the only difference being the
count sequences as noted in the State Diagram Each cir-
cuit contains four master slave flip-flops with internal gat-
ing and steering logic to provide master reset individual pre-
set count up and count down operations
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes
the slave and thus the Q output to change state Synchro-
nous switching as opposed to ripple counting is achieved
by driving the steering gates of all stages from a common
Count Up line and a common Count Down line thereby
causing all state changes to be initiated simultaneously A
LOW-to-HIGH transition on the Count Up input will advance
the count by one a similar transition on the Count Down
input will decrease the count by one While counting with
one clock input the other should be held HIGH Otherwise
the circuit will either count by twos or not at all depending
on the state of the first flip-flop which cannot toggle as long
as either Clock input is LOW
The Terminal Count Up (TC
U
) and Terminal Count Down
(TC
D
) outputs are normally HIGH When a circuit has
reached the maximum count state (9 for the '192 15 for the
'193) the next HIGH-to-LOW transition of the Count Up
Clock will cause TC
U
to go LOW TC
U
will stay LOW until
CP
U
goes HIGH again thus effectively repeating the Count
Up Clock but delayed by two gate delays Similarly the TC
D
output will go LOW when the circuit is in the zero state and
the Count Down Clock goes LOW Since the TC outputs
repeat the clock waveforms they can be used as the clock
input signals to the next higher order circuit in a multistage
counter
TC
U
e
Q0
Q3
CP
U
TC
D
e
Q0
Q1
Q2
Q3
CP
D
Each circuit has an asynchronous parallel load capability
permitting the counter to be reset When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW informa-
tion present on the Parallel Data inputs (P0 P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs A HIGH signal on the
Master Reset input will disable the preset gates override
both Clock inputs and latch each Q output in the LOW
state If one of the Clock inputs is LOW during and after a
reset or load operation the next LOW-to-HIGH transition of
that Clock will be interpreted as a legitimate signal and will
be counted
State Diagram
TL F 10178 4
3
Logic Diagram
TLF10178
3
4
5
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