54AC646
Octal Transceiver/Register with TRI-STATE
Outputs
General Description
The 'AC646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in
Figures 1, 2, 3, 4.
Features
n
Independent registers for A and B buses
n
Multiplexed real-time and stored data transfers
n
TRI-STATE outputs
n
300 mil slim dual-in-line package
n
Outputs source/sink 24 mA
n
'ACT646 has TTL compatible inputs
n
Standard Microcircuit Drawing (SMD)
-- 'AC646: 5962-89682
Logic Symbols
Pin Names
Description
A
0
A
7
Data Register A Inputs
Data Register A Outputs
B
0
B
7
Data Register B Inputs
Data Register B Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Transmit/Receive Inputs
G
Output Enable Input
DIR
Direction Control Input
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
is a registered trademark of Fairchild Semiconductor Corporation.
DS100231-1
IEEE/IEC
DS100231-2
August 1998
54AC646
Octal
T
ransceiver/Register
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100231
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100231-3
Pin Assignment
for LCC
DS100231-4
Real Time Transfer
A-Bus to B-Bus
DS100231-7
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
DS100231-8
FIGURE 2.
Storage from
Bus to Register
DS100231-9
FIGURE 3.
Transfer from
Register to Bus
DS100231-10
FIGURE 4.
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2
Function Table
Inputs
Data I/O (Note 1)
Function
G DIR
CPAB
CPBA
SAB SBA
A
0
A
7
B
0
B
7
H
X
H or L
H or L
X
X
Isolation
H
X
N
X
X
X
Input
Input
Clock A
n
Data into A Register
H
X
X
N
X
X
Clock B
n
Data into B Register
L
H
X
X
L
X
A
n
to B
n
-- Real Time (Transparent Mode)
L
H
N
X
L
X
Input
Output
Clock A
n
Data into A Register
L
H
H or L
X
H
X
A Register to B
n
(Stored Mode)
L
H
N
X
H
X
Clock A
n
Data into A Register and Output to B
n
L
L
X
X
X
L
B
n
to A
n
-- Real Time (Transparent Mode)
L
L
X
N
X
L
Output
Input
Clock B
n
Data into B Register
L
L
X
H or L
X
H
B Register to A
n
(Stored Mode)
L
L
X
N
X
H
Clock B
n
Data into B Register and Output to A
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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Logic Diagram
DS100231-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'AC
2.0V to 6.0V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54AC
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
54AC
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed
Limits
V
IH
Minimum High Level
3.0
2.1
V
OUT
= 0.1V
Input Voltage
4.5
3.15
V
or V
CC
- 0.1V
5.5
3.85
V
IL
Maximum Low Level
3.0
0.9
V
OUT
= 0.1V
Input Voltage
4.5
1.35
V
or V
CC
- 0.1V
5.5
1.65
V
OH
Minimum High Level
3.0
2.9
I
OUT
= -50 A
Output Voltage
4.5
4.4
V
5.5
5.4
(Note 3)
V
IN
= V
IL
or V
IH
3.0
2.4
I
OH
= -12 mA
4.5
3.7
V
I
OH
= -24 mA
5.5
4.7
I
OH
= -24 mA
V
OL
Maximum Low Level
3.0
0.1
I
OUT
= 50 A
Output Voltage
4.5
0.1
V
5.5
0.1
(Note 3)
V
IN
= V
IL
or V
IH
3.0
0.50
I
OH
= 12 mA
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OH
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OLD
Minimum Dynamic
Output Current
(Note 4)
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
5.5
-50
mA
V
OHD
= 3.85V Min
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