TL F 9525
54F74F377
Octal
D
Flip-Flop
with
Clock
Enable
May 1995
54F 74F377
Octal D Flip-Flop with Clock Enable
General Description
The 'F377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop's Q out-
put The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion
Features
Y
Ideal for addressable register applications
Y
Clock enable for address and data synchronization
applications
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
See 'F273 for master reset version
Y
See 'F373 for transparent latch version
Y
See 'F374 for TRI-STATE
version
Y
Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Package Description
Number
74F377PC
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
54F377DM (QB)
J20A
20-Lead Ceramic Dual-In-Line
74F377SC (Note 1)
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
74F377SJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
54F377FM (QB)
W20A
20-Lead Cerpack
54F377LM (QB)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SCX and SJX
Logic Symbols
TL F 9525 1
IEEE IEC
TL F 9525 4
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
TL F 9525 2
Pin Assignment
for LCC
TL F 9525 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
D
0
D
7
Data Inputs
1 0 1 0
20 mA
b
0 6 mA
CE
Clock Enable (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
CP
Clock Pulse Input
1 0 1 0
20 mA
b
0 6 mA
Q
0
Q
7
Data Outputs
50 33 3
b
1 mA 20 mA
Mode Select-Function Table
Operating Mode
Inputs
Output
CP
CE
D
n
Q
n
Load ``1''
L
I
h
H
Load ``0''
L
I
I
L
Hold
L
h
X
No Change
(Do Nothing)
X
H
X
No Change
H
e
HIGH Voltage Level
h
e
HIGH Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
L
e
LOW Voltage Level
I
e
LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
Logic Diagram
TL F 9525 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10% V
CC
2 5
I
OH
e b
1 mA
Voltage
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA
74F 5% V
CC
2 7
I
OH
e b
1 mA
V
OL
Output LOW
54F 10% V
CC
0 5
V
Min
I
OL
e
20 mA
Voltage
74F 10% V
CC
0 5
I
OL
e
20 mA
I
IH
Input HIGH Current
5 0
m
A
Max
V
IN
e
2 7V
I
BVI
Input HIGH Current
7 0
m
A
Max
V
IN
e
7 0V
Breakdown Test
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V
I
CEX
Output HIGH Leakage Current
50
m
A
Max
V
OUT
e
V
CC
V
ID
Input Leakage Test
4 75
V
0 0
I
ID
e
1 9 mA
All Other Pins Grounded
I
OD
Output Leakage Circuit Current
3 75
m
A
0 0
V
IOD
e
150 mV
All Other Pins Grounded
I
CCH
Power Supply Current
35
46
mA
Max
CP
e
L
I
CCL
44
56
D
n
e
MR
e
HIGH
3
AC Electrical Characteristics
74F
54F
74F
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Symbol
Parameter
V
CC
e a
5 0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
Max
Maximum Clock Frequency
130
85
105
MHz
t
PLH
Propagation Delay
3 0
7 0
2 0
8 5
2 5
7 5
ns
t
PHL
CP to Q
n
4 0
9 0
3 0
10 5
3 5
9 0
AC Operating Requirements
74F
54F
74F
Symbol
Parameter
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Units
V
CC
e a
5 0V
Min
Max
Min
Max
Min
Max
t
s
(H)
Setup Time HIGH or LOW
3 0
3 5
3 0
ns
t
s
(L)
D
n
to CP
3 5
4 0
3 5
t
h
(H)
Hold Time HIGH or LOW
0 5
1 0
0 5
ns
t
h
(L)
D
n
to CP
1 0
1 0
1 0
t
s
(H)
Setup Time HIGH or LOW
4 1
4 0
4 1
ns
t
s
(L)
CE to CP
3 5
5 0
4 0
t
h
(H)
Hold Time HIGH to LOW
0 5
1 5
0 5
ns
t
h
(L)
CE to CP
2 0
2 5
2 0
t
w
(H)
Clock Pulse Width
6 0
5 0
6 0
ns
t
w
(L)
HIGH or LOW
6 0
5 0
6 0
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows
74F
377
S
C
X
Temperature Range Family
Special Variations
74F
e
Commercial
X
e
Devices shipped in 13 reels
54F
e
Military
QB
e
Military grade with environmental
and burn-in processing shipped
Device Type
in tubes
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0 C to
a
70 C)
D
e
Ceramic DIP
M
e
Military (
b
55 C to
a
125 C)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
4
5
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S)
NS Package Number M20B
6
Physical Dimensions
inches (millimeters) (Continued)
20-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ)
NS Package Number M20D
7
54F74F377
Octal
D
Flip-Flop
with
Clock
Enable
Physical Dimensions
inches (millimeters) (Continued)
20-Lead (0 300 Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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