54ACT823
9-Bit D Flip-Flop
General Description
The ACT823 is a 9-bit buffered register. It features Clock En-
able and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems. The ACT823
offers noninverting outputs and is fully compatible with
AMD's Am29823.
Features
n
Outputs source/sink 24 mA
n
TRI-STATE outputs for bus interfacing
n
Inputs and outputs are on opposite sides
n
ACT823 has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD) 5962-9161001
Ordering Code
Order Number
Package Number
Package Description
54ACT823DMQB
J24A
24-Lead Ceramic Dual-in-line
54ACT823FMQB
W24C
24-Lead Cerpack
54ACT823LMQB
E28A
28-Lead Ceramic Leadless Chip Carrier, Type C
Logic Symbols
Pin Names
Description
D
0
D
8
Data Inputs
O
0
O
8
Data Outputs
OE
Output Enable
CLR
Clear
CP
Clock Input
EN
Clock Enable
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
TRI-STATE
TM
is a trademark of National Semiconductor Corporation.
DS100253-1
IEEE/IEC
DS100253-2
August 1998
54ACT823
9-Bit
D
Flip-Flop
1998 National Semiconductor Corporation
DS100253
www.national.com
Connection Diagrams
Pin Assignment for DIP
and Cerpack
DS100253-3
Pin Assignment
for LCC
DS100253-4
www.national.com
2
Functional Description
The ACT823 consists of nine D-type edge-triggered
flip-flops. These have TRI-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
buffered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output En-
able pins, there are Clear (CLR) and Clock Enable (EN) pins.
These devices are ideal for parity bus interfacing in high per-
formance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the EN
is HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
Internal
Output
Function
OE
CLR
EN
CP
D
Q
O
H
X
L
N
L
L
Z
High Z
H
X
L
N
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
N
L
L
Z
Load
H
H
L
N
H
H
Z
Load
L
H
L
N
L
L
L
Load
L
H
L
N
H
H
H
Load
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
Logic Diagram
DS100253-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to 7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source or Sink Current
(I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACT
-55C to +125C
Minimum Input Edge Rate (
V/
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
-0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
4.5
0.8
or V
CC
-0.1V
V
OH
Minimum High Level
Output Voltage
4.5
3.7
V
I
OH
= -24 mA
V
OL
Maximum Low Level
Output Voltage
4.5
0.5
V
I
OL
= 24 mA
I
IN
Maximum Input
Leakage Current
5.5
1.0
A
V
I
= V
CC
, GND
I
OZ
Maximum TRI-STATE
5.5
10.0
A
V
I
= V
IL
, V
IH
Current
V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
-2.1V
I
OLD
(Note 3) Minimum
Dynamic Output
Current
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
160
A
V
IN
= V
CC
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
(Note 4)
T
A
= -55C to +125C
C
L
= 50 pF
Units
Min
Max
f
max
Maximum Clock
5.0
95
MHz
Frequency
t
PLH
Propagation Delay
5.0
1.0
12.0
ns
CP to O
n
www.national.com
4
AC Electrical Characteristics
(Continued)
Symbol
Parameter
V
CC
(V)
(Note 4)
T
A
= -55C to +125C
C
L
= 50 pF
Units
Min
Max
t
PHL
Propagation Delay
5.0
1.0
12.0
ns
CP to O
n
t
PHL
Propagation Delay
5.0
1.0
18.0
ns
CLR to O
n
t
PZH
Output Enable Time
5.0
1.0
11.5
ns
OE to O
n
t
PZL
Output Enable Time
5.0
1.0
12.0
ns
OE to O
n
t
PHZ
Output Disable Time
5.0
1.0
13.5
ns
OE to O
n
t
PLZ
Output Disable Time
5.0
1.0
12.0
ns
OE to O
n
Note 4: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
(Note 5)
T
A
= -55C to +125C
C
L
= 50 pF
Units
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
4.0
ns
D to CP
t
h
Hold Time, HIGH or LOW
5.0
3.0
ns
D
n
to CP
t
s
Setup Time, HIGH or LOW
5.0
4.0
ns
EN to CP
t
h
Hold Time, HIGH or LOW
5.0
3.0
ns
EN to CP
t
w
CP Pulse Width
5.0
6.0
ns
HIGH or LOW
t
w
CLR Pulse Width, LOW
5.0
7.5
ns
t
rec
CLR to CP
5.0
4.5
ns
Recovery Time
Note 5: Voltage Range 5.0 is 5.0V
0.5V
5
www.national.com
PDF 
ZIP