54ACQ373
54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE
Outputs
General Description
The
'ACQ/'ACTQ373
consists
of
eight
latches
with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The 'ACQ/'ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
TM
features
GTO
TM
output control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch up immunity
n
Eight latches in a single package
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard 'AC/'ACT373
n
4 kV minimum ESD immunity ('ACQ)
n
Standard Military Drawing (SMD)
-- 'ACTQ373: 5962-92188
-- 'ACQ373: 5962-92178
Logic Symbols
Pin Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O
0
O
7
TRI-STATE Latch Outputs
GTO
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100238-1
IEEE/IEC
DS100238-2
September 1998
54ACQQ373
54ACTQ373
Quiet
Series
Octal
T
ransparent
Latch
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100238
www.national.com
Connection Diagrams
Functional Description
The 'ACQ/'ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
Outputs
LE
OE
D
n
O
n
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
Logic Diagram
Pin Assignment for
DIP and Flatpak
DS100238-3
Pin Assignment
for LCC
DS100238-4
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latchup Source
or Sink Current
300 mA
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACQ
2.0V to 6.0V
'ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACQ/ACTQ
-55C to +125C
Minimum Input Edge Rate
V/
t
'ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate
V/
t
'ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note: All commercial packaging is not recommended for applications requir-
ing greater than 2000 temperature cycles from -40C to +125C.
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
circuits outside databook specifications.
DC Characteristics for 'ACQ Family Devices
54ACQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
3.0
2.1
V
OUT
= 0.1V
Input Voltage
4.5
3.15
V
or V
CC
- 0.1V
5.5
3.85
V
IL
Maximum Low Level
3.0
0.9
V
OUT
= 0.1V
Input Voltage
4.5
1.35
V
or V
CC
- 0.1V
5.5
1.65
V
OH
Minimum High Level
3.0
2.9
I
OUT
= -50 A
Output Voltage
4.5
4.4
V
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
3.0
2.4
I
OH
= -12 mA
4.5
3.7
V
I
OH
= -24 mA
5.5
4.7
I
OH
= -24 mA
V
OL
Maximum Low Level
3.0
0.1
I
OUT
= 50 A
Output Voltage
4.5
0.1
V
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
3.0
0.50
I
OL
= 12 mA
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
(Note 4)
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3
DC Characteristics for 'ACQ Family Devices
(Continued)
54ACQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
I
OLD
Minimum Dynamic
(Note 3)
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Output Current
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND (Note 4)
I
OZ
Maximum TRI-STATE
V
I
(OE) = V
IL
, V
IH
Leakage Current
5.5
5.0
A
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLP
Quiet Output
5.0
1.5
V
Maximum Dynamic V
OL
(Notes 5, 6)
V
OLV
Quiet Output
5.0
-1.2
V
Maximum Dynamic V
OL
(Notes 5, 6)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54ACQ
@
25C is identical to 74ACQ
@
25C.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output
@
GND.
Note 7: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 5V ('ACQ). Input-under-test switching: 5V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
DC Characteristics for 'ACTQ Family Devices
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 8)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 8)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OZ
Maximum TRI-STATE
5.5
5.0
A
V
I
= V
IL
, V
IH
Leakage Current
V
O
= V
CC
, GND
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4
DC Characteristics for 'ACTQ Family Devices
(Continued)
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
I
CCT
Maximum
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Output Current
(Note 9)
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND (Note 10)
V
OLP
Quiet Output
5.0
1.5
V
Maximum Dynamic V
OL
(Notes 11, 12)
V
OLV
Quiet Output
5.0
-1.2
V
Minimum Dynamic V
OL
(Notes 11, 12)
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: I
CC
for 54ACTQ
@
25C is identical to 74ACTQ
@
25C.
Note 11: Plastic DIP package.
Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
@
GND.
AC Electrical Characteristics
V
CC
(V)
(Note 13)
54ACQ
T
A
= -55C
Symbol
Parameter
to +125C
Units
C
L
= 50 pF
Min
Max
t
PHL
, t
PLH
Propagation Delay
3.3
1.0
15.0
ns
D
n
to O
n
5.0
1.0
9.5
t
PHL
, t
PLH
Propagation Delay
3.3
1.0
16.0
ns
LE to O
n
5.0
1.0
9.5
t
PZL
, t
PZH
Output Enable Time
3.3
1.0
14.5
ns
5.0
1.0
10.5
t
PHZ
, t
PLZ
Output Disable Time
3.3
1.0
12.0
ns
5.0
1.0
10.5
Note 13: Voltage Range 5.0 is 5.0V
0.5V.
Voltage Range 3.3 is 3.3V
0.3V.
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5
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
(Note 14)
54ACQ
Units
T
A
= -55C
to +125C
C
L
= 50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
3.3
3.0
ns
D
n
to LE
5.0
3.0
t
h
Hold Time, HIGH or LOW
3.3
1.5
ns
D
n
to LE
5.0
1,5
t
w
LE Pulse Width, HIGH
3.3
5.0
ns
5.0
5.0
Note 14: Voltage Range 5.0 is 5.0V
0.5V.
Voltage Range 3.3 is 3.3V
0.3V.
AC Electrical Characteristics
V
CC
(V)
(Note 15)
54ACTQ
T
A
= -55C
Symbol
Parameter
to +125C
Units
C
L
= 50 pF
Min
Max
t
PHL
, t
PLH
Propagation Delay
5.0
1.5
10.5
ns
D
n
to O
n
t
PHL
, t
PLH
Propagation Delay
5.0
1.5
11.5
ns
LE to O
n
t
PZL
, t
PZH
Output Enable Time
5.0
1.5
11.0
ns
t
PHZ
, t
PLZ
Output Disable Time
5.0
1.5
10.5
ns
Note 15: Voltage Range 5.0 is 5.0V
0.5V.
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
(Note 16)
54ACTQ
Units
T
A
= -55C
to +125C
C
L
= 50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
3.5
ns
D
n
to LE
t
h
Hold Time, HIGH or LOW
5.0
1.5
ns
D
n
to LE
t
w
LE Pulse Width, HIGH
5.0
5.0
ns
Note 16: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation
44.0
pF
V
CC
= 5.0V
Capacitance
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6
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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7
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fax: 81-3-5620-6179
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
54ACQQ373
54ACTQ373
Quiet
Series
Octal
T
ransparent
Latch
with
TRI-ST
A
T
E
Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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