54ABT543
Octal Registered Transceiver with TRI-STATE
Outputs
General Description
The 'ABT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direc-
tion. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow.
Features
n
Back-to-back registers for storage
n
Bidirectional data path
n
A and B outputs have current sourcing capability of 24
mA and current sinking capability of 48 mA
n
Separate controls for data flow in each direction
n
Guaranteed latchup protection
n
High impedance glitch free bus loading during entire
power up and power down cycle
n
Nondestructive hot insertion capability
n
Standard Military Drawing (SMD) 5962-9231401
Ordering Code:
Military
Package
Package Description
Number
54ABT543J-QML
J24F
24-Lead Ceramic Dual-In-Line
54ABT543W-QML
W24C
24-Lead Cerpack
54ABT543E-QML
E28A
28-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment for
DIP and Flatpak
10021801
Pin Assignment
for LCC
10021802
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
November 2002
54ABT543
Octal
Registered
T
ransceiver
with
TRI-ST
A
T
E
Outputs
2002 National Semiconductor Corporation
DS100218
www.national.com
Pin Descriptions
Pin Names
Description
OEAB , OEBA
Output Enable Inputs
LEAB , LEBA
Latch Enable Inputs
CEAB , CEBA
Chip Enable Inputs
A
0
A
7
Side A Inputs or
TRI-STATE Outputs
B
0
B
7
Side B Inputs or
TRI-STATE Outputs
Functional Description
The 'ABT543 contains two sets of D-type latches, with sepa-
rate input and output controls for each. For data flow from A
to B, for example, the A to B Enable (CEAB ) input must be
low in order to enter data from the A port or take data from
the B port as indicated in the Data I/O Control Table. With
CEAB low, a low signal on (LEAB ) input makes the A to B
latches transparent; a subsequent low to high transition of
the LEAB line puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB
and OEAB both low, the B output buffers are active and
reflect the data present on the output of the A latches.
Control of data flow from B to A is similar, but using the
CEBA , LEBA and OEBA .
Data I/O Control Table
Inputs
Latch Status
Output
Buffers
CEAB
LEAB
OEAB
H
X
X
Latched
High Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
High Z
L
X
L
--
Driving
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Logic Diagram
10021803
54ABT543
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0
mA
Voltage Applied to Any Output
in the Disable or Power-Off State
-0.5V to +5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
DC Electrical Characteristics
Symbol
Parameter
ABT543
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA (Non I/O Pins)
V
OH
Output HIGH Voltage
54ABT
2.5
I
OH
= -3 mA, (A
n
, B
n
)
54ABT
2.0
V
Min
I
OH
= -24 mA, (A
n
, B
n
)
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA, (A
n
, B
n
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A, (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Non-I/O Pins)
(Note 3)
V
IN
= V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
= 7.0V (Non-I/O Pins)
I
BVIT
Input HIGH Current
100
A
Max
V
IN
= 5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Non-I/O Pins)(Note
3)
V
IN
= 0.0V (Non-I/O Pins)
I
IH
+ I
OZH
Output Leakage Current
50
A
0V5.5V V
OUT
= 2.7V (A
n
, B
n
);
OEAB or CEAB = 2V
I
IL
+ I
OZL
Output Leakage Current
-50
A
0V5.5V V
OUT
= 0.5V (A
n
, B
n
);
OEAB or CEAB = 2V
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
= V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
= 5.5V (A
n
, B
n
);
All Others GND
I
CCLH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
Outputs TRI-STATE
All Others at V
CC
or GND
54ABT543
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3
DC Electrical Characteristics
(Continued)
Symbol
Parameter
ABT543
Units
V
CC
Conditions
Min
Typ
Max
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
Outputs Open, CEAB
(Note 3)
0.18
mA/MHz
Max
and OEAB = GND,CEBA =
V
CC
, One Bit Toggling,
50% Duty Cycle, (Note 4)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: Guaranteed but not tested.
Note 4: For 8-bit toggling. I
CCD
<
1.4 mA/MHz.
DC Electrical Characteristics
Conditions
Symbol
Parameter
Min
Max
Units
V
CC
C
L
= 50 pF,
R
L
= 500
V
OLP
Quiet Output Maximum Dynamic V
OL
1.1
V
5.0
T
A
= 25C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
-0.45
V
5.0
T
A
= 25C(Note 5)
Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW.
AC Electrical Characteristics
54ABT
T
A
= -55C to +125C
Fig.
Symbol
Parameter
V
CC
= 4.5V5.5V
Units
No.
C
L
= 50 pF
Min
Max
t
PLH
Propagation Delay
1.6
6.4
ns
Figure
4
t
PHL
A
n
to B
n
or B
n
to A
n
1.6
6.2
t
PLH
Propagation Delay
t
PHL
LEAB to B
n
, LEBA to A
n
1.6
6.6
ns
Figure
4
OEBA or OEAB to A
n
or
B
n
1.6
6.4
t
PZH
Enable Time
t
PZL
LEAB to B
n
, LEBA to A
n
1.3
6.4
ns
Figure
6
OEBA or OEAB to A
n
or
B
n
1.8
7.4
t
PHZ
Disable Time
2.0
7.2
ns
Figure
6
t
PLZ
CEBA or CEAB to A
n
or
B
n
1.5
7.0
54ABT543
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4
AC Operating Requirements
54ABT
T
A
= -55C to +125C
Fig.
Symbol
Parameter
V
CC
= 4.5V5.5V
Units
No.
C
L
= 50 pF
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
3.5
ns
Figure
7
t
S
(L)
A
n
or B
n
to LEBA or LEAB
3.0
t
H
(H)
Hold Time, HIGH or LOW
2.0
ns
Figure
7
t
H
(L)
A
n
or B
n
to LEBA or LEAB
2.0
t
S
(H)
Setup Time, HIGH or LOW
3.3
ns
Figure
7
t
S
(L)
A
n
or B
n
to CEAB or CEBA
2.5
t
H
(H)
Hold Time, HIGH or LOW
2.0
ns
Figure
7
t
H
(L)
A
n
or B
n
to CEAB or CEBA
2.0
t
W
(L)
Pulse Width, LOW
3.5
ns
Figure
5
Capacitance
Symbol
Parameter
Typ
Units
Conditions: T
A
= 25C
C
IN
Input Capacitance
5.0
pF
V
CC
= 0V (non I/O pins)
C
I/O
(Note 6)
Output Capacitance
11.0
pF
V
CC
= 5.0V (A
n
, B
n
)
Note 6: C
I/O
is measured at frequency, f = 1 MHz, PER MIL-STD-883, METHOD 3012.
AC Loading
10021804
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
10021806
FIGURE 2. V
M
= 1.5V
Input Pulse Requirements
Amplitude Rep. Rate
t
w
t
r
t
f
3V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
54ABT543
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5
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