TL W 12459
LMX2305
PLLatinum
550
MHz
Frequency
Synthesizer
for
RF
Personal
Communications
PRELIMINARY
August 1996
LMX2305
PLLatinum
TM
550 MHz Frequency Synthesizer
for RF Personal Communications
General Description
The LMX2305 is a high performance frequency synthesizer
with an integrated prescaler designed for RF operation up to
550 MHz It is fabricated using National's ABiC IV BiCMOS
process
The LMX2305 contains a dual modulus prescaler which can
select either a 64 65 or a 128 129 divide ratio at input fre-
quencies of up to 550 MHz LMX2305 which employs the
digital phase lock loop technique combined with a high
quality reference oscillator and a loop filter provides the
tuning voltage for the voltage controlled oscillator to gener-
ate a very stable low noise local oscillator signal
Serial data is transferred into the LMX2305 via a three line
MICROWIRE
TM
interface (Data Enable Clock) Supply volt-
age can range from 2 65V to 5 5V The LMX2305 features
very low current consumption typically 4 0 mA at 2 75V
The LMX2305 is available in a TSSOP 20-pin surface mount
plastic package
Features
Y
RF operation up to 550 MHz
Y
2 65V to 5 5V operation
Y
Low current consumption
I
CC
e
4 0 mA (typ) at V
CC
e
2 75V
Y
Dual modulus prescaler 64 65 or 128 129
Y
Internal balanced low leakage charge pump
Y
Small-outline plastic surface mount TSSOP
0 173
wide package
Applications
Y
Analog Cellular telephone systems
(AMPS ETACS NMT)
Y
Portable wireless communications
(PCS PCN cordless)
Y
Wireless local area networks (WLANs)
Y
Other wireless communication systems
Y
Pagers
Block Diagram
TL W 12459 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
and PLLatinum
TM
are trademarks of National Semiconductor Corporation
C1996 National Semiconductor Corporation
RRD-B30M126 Printed in U S A
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Connection Diagram
LMX2305
TL W 12459 2
20-Lead (0 173 Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX2305TM or LMX2305TMX
See NS Package Number MTC20
Pin Descriptions
Pin No
Pin Name
I O
Description
1
OSC
IN
I
Oscillator input A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator The input has a V
CC
2 input threshold and can be driven from an
external CMOS or TTL logic gate May also be from a reference oscillator
3
OSC
OUT
O
Oscillator output
4
V
P
Power supply for charge pump Must be
t
V
CC
5
V
CC
Power supply voltage input Input may range from 2 65V to 5 5V Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane
6
D
o
O
Internal charge pump output For connection to a loop filter for driving the input of an external
VCO
7
GND
Ground
8
LD
O
Lock detect Output provided to indicate when the VCO frequency is in ``lock'' When the loop is
locked the pin's output is HIGH with narrow low pulses
10
f
IN
I
Prescaler input Small signal input from the VCO
11
CLOCK
I
High impedance CMOS Clock input Data is clocked in on the rising edge into the various
counters and registers
13
DATA
I
Binary serial data input Data entered MSB first LSB is control bit High impedance CMOS input
14
LE
I
Load enable input (with internal pull-up resistor) When LE transitions HIGH data stored in the
shift registers is loaded into the appropriate latch (control bit dependent) Clock must be low
when LE toggles high or low See Serial Data Input Timing Diagram
15
FC
I
Phase control select (with internal pull-up resistor) When FC is LOW the polarity of the phase
comparator and charge pump combination is reversed
16
BISW
O
Analog switch output When LE is HIGH the analog switch is ON routing the internal charge
pump output through BISW (as well as through D
o
)
17
f
OUT
O
Monitor pin of phase comparator input CMOS output
18
w
p
O
Output for external charge pump w
p
is an open drain N-channel transistor and requires a pull-up
resistor
19
PWDN
I
Power Down (with internal pull-up resistor)
PWDN
e
HIGH for normal operation
PWDN
e
LOW for power saving
Power down function is gated by the return of the charge pump to a TRI-STATE condition
20
w
r
O
Output for external charge pump w
r
is a CMOS logic output
2 9 12
NC
No connect
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Functional Block Diagram
TL W 12459 3
Note 1
The power down function is gated by the charge pump to prevent any unwanted frequency jumps Once the power down pin is brought low the part will go
into power down mode when the charge pump reaches a TRI-STATE condition
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Absolute Maximum Ratings
(Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Power Supply Voltage
V
CC
b
0 3V to
a
6 5V
V
P
b
0 3V to
a
6 5V
Voltage on Any Pin
with GND
e
0V (V
I
)
b
0 3V to V
CC
a
0 3V
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Lead Temperature (T
L
) (solder 4 sec )
a
260 C
Recommended Operating
Conditions
Power Supply Voltage
V
CC
2 65V to 5 5V
V
P
V
CC
to
a
5 5V
Operating Temperature (T
A
)
b
40 C to
a
85 C
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur Operating Ratings indicate conditions for which the
device is intended to be functional but do not guarantee specific perform-
ance limits For guaranteed specifications and test conditions see the Elec-
trical Characteristics The guaranteed specifications apply only for the test
conditions listed
Note 2
This device is a high performance RF integrated circuit with an ESD
rating
k
2 keV and is ESD sensitive Handling and assembly of this device
should only be done at ESD workstations
Electrical Characteristics
V
CC
e
2 75V V
P
e
2 75V
b
40 C
k
T
A
k
85 C except as specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current
4
6
mA
I
CC-PWDN
Power Down Current
30
180
m
A
f
IN
RF Input Operating Frequency
45
550
MHz
f
OSC
Oscillator Input Operating Frequency
5
22
MHz
f
w
Phase Detector Frequency
10
MHz
Pf
IN
Input Sensitivity
V
CC
e
2 65V to 5 5V
b
10
a
6
dBm
V
OSC
Oscillator Sensitivity
OSC
IN
0 5
V
PP
V
IH
High-Level Input Voltage
0 7 V
CC
V
V
IL
Low-Level Input Voltage
0 3 V
CC
V
I
IH
High-Level Input Current (Clock Data)
V
IH
e
V
CC
e
5 5V
b
1 0
1 0
m
A
I
IL
Low-Level Input Current (Clock Data)
V
IL
e
0V V
CC
e
5 5V
b
1 0
1 0
m
A
I
IH
Oscillator Input Current
V
IH
e
V
CC
e
5 5V
100
m
A
I
IL
V
IL
e
0V V
CC
e
5 5V
b
100
m
A
I
IH
High-Level Input Current (LE FC)
V
IH
e
V
CC
e
5 5V
b
1 0
1 0
m
A
I
IL
Low-Level Input Current (LE FC)
V
IL
e
0V V
CC
e
5 5V
b
100
1 0
m
A
Except f
IN
and OSC
IN
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Electrical Characteristics
V
CC
e
2 75V V
P
e
2 75V
b
40 C
k
T
A
k
85 C except as specified (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
Do-source
Charge Pump Output Current
V
Do
e
V
P
2
b
2 5
b
1 0
mA
I
Do-sink
V
Do
e
V
P
2
1 0
2 5
mA
I
Do-Tri
Charge Pump TRI-STATE Current
0 5V
s
V
Do
s
V
P
b
0 5V
b
5 0
5 0
nA
T
A
e b
40 C
k
T
A
k
85 C
V
OH
High-Level Output Voltage
I
OH
e b
1 0 mA
V
CC
b
0 8
V
V
OL
Low-Level Output Voltage
I
OL
e
1 0 mA
0 4
V
V
OH
High-Level Output Voltage (OSC
OUT
)
I
OH
e b
200 mA
V
CC
b
0 8
V
V
OL
Low-Level Output Voltage (OSC
OUT
)
I
OL
e
200 mA
0 4
V
I
OL
Open Drain Output Current (w
p
)
V
OL
e
0 4V
1 0
mA
I
OH
Open Drain Output Current (w
p
)
V
OH
e
2 75V
100
m
A
t
CS
Data to Clock Set Up Time
See Data Input Timing
50
ns
t
CH
Data to Clock Hold Time
See Data Input Timing
10
ns
t
CWH
Clock Pulse Width High
See Data Input Timing
50
ns
t
CWL
Clock Pulse Width Low
See Data Input Timing
50
ns
t
ES
Clock to Enable Set Up Time
See Data Input Timing
50
ns
t
EW
Enable Pulse Width
See Data Input Timing
50
ns
Except OSC
OUT
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