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Электронный компонент: 74ABT3284

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TL F 11582
74ABT3284
18-Bit
Synchronous
Datapath
Multiplexer
October 1995
74ABT3284
18-Bit Synchronous Datapath Multiplexer
General Description
The 74ABT3284 is a synchronous datapath buffer designed
to transmit four 9-bit bytes of data onto one or two 9-bit
bytes in 2 1 or 4 1 multiplexed configurations In addition
the non-inverting transceiver supports bidirectional data
transfer in transparent or registered modes A data byte
from any one of the six ports can be stored during transpar-
ent operation for later recall Data input to any port may also
be read back to itself for byte manipulation or system self-di-
agnostic purposes
The 74ABT3284 is useful for interleaving data in memory
applications or for use in bus-to-bus communications where
variations in data word length or construction are required
Features
Y
Advanced BiCMOS technology provides high speed at
low power consumption
Y
18-bit 2 1 or 9-bit 4 1 multiplexed modes
Y
Registered or transparent datapath operation
Y
Output enables and select lines have the option of be-
ing synchronized for pipelined operation
Y
Independent input output register and control synchro-
nizing clocks insure maximum timing flexibility
Y
Independent control signals insure functional flexibility
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Y
Guaranteed latchup protection
Y
High impedance glitch free bus loading during entire
power up and power down cycle
Y
Non-destructive hot insertion capability
Commercial
Package Number
Package Description
74ABT3284VJG
VJG100A
100-Lead (14mm x 14mm) Molded Plastic Quad Flatpak JEDEC
Connection Diagram
TL F 11582 1
Pin Assignment
Pin
Pin
Pin
Pin
1
Mode
SO
26
V
CC
51
CP
IN
76
V
CC
2
CP
AX
27
A
8
52
OEB
77
D
8
3
OEC
28
A
7
53
LDBI
78
D
7
4
LDCI
29
A
6
54
LDBO
79
D
6
5
LDCO
30
GND
55
Mode
W
80
GND
6
SA
2
X
1
31
A
5
56
YSEL
81
D
5
7
SA
2
X
0
32
A
4
57
OEY
82
D
4
8
X
0
33
A
3
58
Y
8
83
D
3
9
X
1
34
A
2
59
Y
7
84
D
2
10
GND
35
GND
60
GND
85
GND
11
X
2
36
A
1
61
Y
6
86
D
1
12
X
3
37
A
0
62
Y
5
87
D
0
13
X
4
38
V
CC
63
Y
4
88
V
CC
14
X
5
39
B
0
64
Y
3
89
C
0
15
X
6
40
B
1
65
Y
2
90
C
1
16
GND
41
GND
66
GND
91
GND
17
X
7
42
B
2
67
Y
1
92
C
2
18
X
8
43
B
3
68
Y
0
93
C
3
19
OEX
44
B
4
69
LDDO
94
C
4
20
XSEL
0
45
B
5
70
LDDI
95
C
5
21
XSEL
1
46
GND
71
ASEL1
96
GND
22
LDAO
47
B
6
72
ASEL0
97
C
6
23
LDAI
48
B
7
73
OED
98
C
7
24
OEA
49
B
8
74
CP
XA
99
C
8
25
V
CC
50
V
CC
75
Mode
SC
100
V
CC
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M125 Printed in U S A
Functional Description
The 74ABT3284 is a bi-directional registered data-path rout-
ing device which can multiplex de-multiplex four 9-bit ``A-
side'' data ports (Ports A B C D) onto from one 9-bit ``X-
side'' port (Port X) Alternatively it can be configured for
mux demux of two 18-bit data paths (Ports A and C B and
D) onto from one 18-bit data path (Ports X and Y)
Each of the six 9-bit I O ports have independent active low
TRI-STATE
output enable control logic which can be con-
figured to operate asynchronously or synchronously With
MODE
SO low direct asynchronous output control is pro-
vided With MODE
SO high output enable control is as-
serted synchronously on the positive edge of the CP
IN
clock All I O port inputs are continuously active allowing
output state feedback
The four A-side ports (A B C D) contain independently
enabled input and output data registers for storage of data
passing in either direction The input register (AIR BIR CIR
DIR) is loaded held on the positive edge of CP
AX when
the respective Load Control pin (LDAI LDBI LDCI LDDI) is
asserted high low The Input Registers can be loaded with
data from the corresponding A-side port The output register
(AOR BOR COR DOR) is loaded held on the positive
edge of CP
XA when the respective Load Control pin
(LDAO LDBO LDCO LDDO) is asserted high low The
Output Registers can be loaded with data from Port X when
MODE
WS is asserted low When MODE
WS is asserted
high the Output Registers A and C can be loaded with Port
X data and the B and D Output Registers can be loaded with
data from Port Y
When routing data from A-side to X-side Data Path Control
is provided for the following options via the SA2X inputs
Transparent mode where Input Register is bypassed but
can simultaneously monitor A-side data Registered Mode
where X-side receives data from the selected Input Regis-
ters Readback Mode where X-side receives data from the
selected Output Registers A-side data from Ports A B C
or D can be selected to Port X via the XSEL data path select
inputs Ports B or D can be selected to Port Y via the YSEL
data path select input
When routing data from X-side to A-side Data Path Control
is provided for the following options via the ASEL inputs
Transparent mode where Output Register is bypassed but
can simultaneously monitor X-side data Registered Mode
where the A-side Port receives data from the corresponding
Output Register Readback Mode where the A-side Port re-
ceives data from the corresponding Input Registers
MODE
WS asserted low selects Port X data to be passed
to Ports A B C and D With MODE
WS asserted high
Port X data is passed to Ports A and C with Port Y data
passed to Ports B and D
All Data Path Control Inputs and Input Output Register
Load Enable Inputs are active high and can be asserted
asynchronously or synchronously When MODE
SC is low
these inputs operate asynchronously When MODE
SC is
high the inputs are asserted synchronously on the positive
edge of the CP
IN clock
When operating the Data Path Control and or the Output
Enable Input groups with MODE
SC and or MODE
SO
``hard wired'' high for synchronous mode a single pre-clock
of CP
IN will be required following power-up to insure that
all internal synchronous control registers are in the appropri-
ate known state if the application requires ``on the fly'''
changes from asynchronous to synchronous operation
then the respective control enable pin data must be pre-
clocked via CP
IN and held steady prior to and during any
low to high transition of the MODE
SO or MODE
SC to
properly initiate the sync control registers for synchronous
control mode
Pin Descriptions
Pin Name
Description
Operation
OEa
Output Enable Inputs
Sync Async
(Active Low)
LDaI
Load Enable Inputs for the
Sync Async
Input Registers
LDaO
Load Enable Inputs for the
Sync Async
Output Registers
ASEL(0 1)
A-Side Data Path Select Inputs
Sync Async
SA2X(0 1)
X-Side Data Path Select Inputs
Sync Async
XSEL(0 1)
X-Port Data Path Select Inputs
Sync Async
YSEL
Y-Port Data Path Select Input
Sync Async
MODE
W
Word Mode Select Input for
Sync Async
the X Y to A-Side Direction
MODE
SO Enable Input for Synchronous
Async
Output Enable Control
MODE
SC Enable Input for Synchronous
Async
Data Path Control
CP
IN
Clock Input for Synchronous
Control (Positive Edge Trigger)
CP
AX
Clock Input for Input Registers
(Positive Edge Trigger)
CP
XA
Clock Input for Output Registers
(Positive Edge Trigger)
2
Function Tables
Output Enable Control Table
Inputs
Outputs
Control
Mode
Function
OE (A B C D X Y)
MODE
SO
CP
IN
Port
A B C D X Y
L
L
X
ENABLE
ASYNC
ENABLED OUTPUT I O input always active
H
L
X
DISABLE
ASYNC
DISABLED OUTPUT I O input always active
(Notes 2 3)
H (Note 1)
L
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SO must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs OE (A B C D X Y) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to
synchronous
Note 2
OE (A B C D X Y) levels are synchronously asserted by the positive transition of CP
IN when MODE
SO is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
A Side Data Path Select Function Table
Inputs
Data Path
Control
Mode
Function
ASEL(1)
ASEL(0)
MODE
SC
CP
IN
From
To
Reg Port
Port
L
L
L
X
(A B C D) IR
A B C D
ASYNC
Readback Contents of Input Register
(A B C D) IR to Port (A B C D)
L
H
L
X
(A B C D) OR
A B C D
ASYNC
Clocked Path Contents of Output
Register (A B C D) OR to Port (A B
C D)
H
L
L
X
Port X
A B C
D
ASYNC
Transparent Path Port X to Port A B
C
D
H
H
L
X
Port X
A
C
ASYNC
Transparent Path Port X to Port A
C
Port Y
B
D
Transparent Path Port Y to Port B
D
(Notes 2 3)
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SC must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs ASEL(0) and ASEL(1) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to
synchronous
Note 2
ASEL(0) and ASEL(1) levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
Input Register Control Table
Inputs
Register
Control
Mode
Function
Port
LD(A B C D) I
MODE
SC
CP
IN
CP
XA
(A B C D) IR
(A B C D)
X
L
L
X
L
HOLD
ASYNC
HOLD Input Register holds previous
state
L (H)
H
L
X
L
L (H)
ASYNC
LOAD Port A B C D clocked to Input
Register (A B C D) IR via CP
AX
positive edge
(Note 3)
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SO must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs LDAI LDBI LDCI and LDDI steady to preset internal registers and assure predictable operation during the control mode change from asynchronous
to synchronous
Note 2
LDAI LDBI LDCI and LDDI levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
3
Function Tables
(Continued)
Output Register Control Table
Inputs
Output Register
Control
Mode
Function
Port X
Port Y
LD(A B C D) O
MODE
W
MODE
SC
CP
IN
CP
XA
(A C) OR
(B D) OR
X
X
L
X
L
X
L
HOLD
HOLD
ASYNC
HOLD
OR
L (H)
X
H
L
L
X
L
L (H)
L (H)
ASYNC
LOAD
OR
Port X to
OR (A B
C D)
L (H)
L (H)
H
H
L
X
L
L (H)
L (H)
ASYNC
LOAD
OR
Port X to
OR
(A C)
Port Y
to OR
(B D)
(Note 3)
(Note 3)
(Notes 2 3)
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SC must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs LDAO LDBO LDCO LDDO and MODE
W steady to preset internal registers and assure predictable operation during the control mode change
from asynchronous to synchronous
Note 2
LDAO LDBO LDCO LDDO and MODE
W levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
4
Function Tables
(Continued)
1st Level X Side Data Path Select Function Table
Inputs
Data Path
Control
Mode
Function
SA2X(1)
SA2X(0)
MODE
SC
CP
IN
From
To
Reg Port
Internal Node
L
L
L
X
A B C D
(A B C D) X
ASYNC
Transparent datapath from Port (A
B C D) to internal node (A B C
D) X
L
H
L
X
(A B C D) IR
(A B C D) X
ASYNC
Clocked Path Contents of Input
Register (A B C D) IR to internal
node (A B C D) X
H
L
L
X
(A B C D) OR
(A B C D) X
ASYNC
Readback contents of Output
register (A B C D) OR to internal
node (A B C D) X
H
H
L
X
GND
(A B C D) X
ASYNC
Diagnostic Select all 36 bits as low
and pass to the internal node (A
B C D) X
(Notes 2 3)
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SC must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs SA2X(0) and SA2X(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous
to synchronous
Note 2
SA2X(0) and SA2X(1) levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
2nd Level X Side Data Path Select Function Table for Port X
Inputs
Data Path
Control
Mode
Function
XSEL(1)
XSEL(0)
MODE
SC
CP
IN
From
To
Internal Node
Port
L
L
L
X
AX
X
ASYNC
Internal Node AX to Port X
L
H
L
X
BX
X
ASYNC
Internal Node BX to Port X
H
L
L
X
CX
X
ASYNC
Internal Node CX to Port X
H
H
L
X
DX
X
ASYNC
Internal Node DX to Port X
(Notes 2 3)
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SC must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs XSEL(0) and XSEL(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous
to synchronous
Note 2
XSEL(0) and XSEL(1) levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
2nd Level X Side Data Path Select Function Table for Port Y
Inputs
Data Path
Control
Mode
Function
YSEL
MODE
SC
CP
IN
From
To
Internal Node
Port
L
L
X
BX
Y
ASYNC
Internal Node BX to Port Y
H
L
X
DX
Y
ASYNC
Internal Node DX to Port Y
(Notes 2 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1
Low to High transitions of MODE
SC must be immediately preceeded by a low to high transition (clock edge) on CP
IN while holding Synchronous
Control Inputs YSEL steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous
Note 2
YSEL levels are synchronously asserted by the positive transition of CP
IN when MODE
SC is high
Note 3
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CP
IN
5