TL F 9516
54F74F322
Octal
SerialParallel
Register
with
Sign
Extend
May 1995
54F 74F322
Octal Serial Parallel Register with Sign Extend
General Description
The 'F322 is an 8-bit shift register with provision for either
serial or parallel loading and with TRI-STATE
parallel out-
puts plus a bi-state serial output Parallel data inputs and
parallel outputs are multiplexed to minimize pin count State
changes are initiated by the rising edge of the clock Four
synchronous modes of operation are possible hold (store)
shift right with serial entry shift right with sign extend and
parallel load An asynchronous Master Reset (MR) input
overrides clocked operation and clears the register
Features
Y
Multiplexed parallel I O ports
Y
Separate serial input and output
Y
Sign extend function
Y
TRI-STATE outputs for bus applications
Commercial
Military
Package
Package Description
Number
74F322PC
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
54F322DM (Note 2)
J20A
20-Lead Ceramic Dual-In-Line
74F322SJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
54F322FM (Note 2)
W20A
20-Lead Cerpack
54F322LM (Note 2)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
TL F 9516 3
IEEE IEC
TL F 9516 5
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
TL F 9516 1
Pin Assignment
for LCC
TL F 9516 2
2
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
RE
Register Enable Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
S P
Serial (HIGH) or Parallel (LOW) Mode Control Input
1 0 1 0
20 mA
b
0 6 mA
SE
Sign Extend Input (Active LOW)
1 0 3 0
20 mA
b
1 8 mA
S
Serial Data Select Input
1 0 2 0
20 mA
b
1 2 mA
D
0
D
1
Serial Data Inputs
1 0 1 0
20 mA
b
0 6 mA
CP
Clock Pulse Input (Active Rising Edge)
1 0 1 0
20 mA
b
0 6 mA
MR
Asynchronous Master Reset Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
OE
TRI-STATE Output Enable Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
Q
0
Bi-State Serial Output
50 33 3
b
1 mA
b
20 mA
I O
0
I O
7
Multiplexed Parallel Data Inputs or
3 5 1 083
70 mA
b
0 65 mA
TRI-STATE Parallel Data Outputs
150 40 (33 3)
b
3 mA 24 mA (20 mA)
Functional Description
The 'F322 contains eight D-type edge triggered flip-flops
and the interstage gating required to perform right shift and
the intrastage gating necessary for hold and synchronous
parallel load operations A LOW signal on RE enables shift-
ing or parallel loading while a HIGH signal enables the hold
mode A HIGH signal on S P enables shift right while a
LOW signal disables the TRI-STATE output buffers and en-
ables parallel loading In the shift right mode a HIGH signal
on SE enables serial entry from either D
0
or D
1
as deter-
mined by the S input A LOW signal on SE enables shift right
but Q
7
reloads its contents thus performing the sign extend
function required for the 'F384 Twos Complement Multiplier
A HIGH signal on OE disables the TRI-STATE output buff-
ers regardless of the other control inputs In this condition
the shifting and loading operations can still be performed
Mode Select Table
Mode
Inputs
Outputs
Q
0
MR
RE
S P
SE
S
OE
CP
I O
7
I O
6
I O
5
I O
4
I O
3
I O
2
I O
1
I O
0
Clear
L
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
X
Z
Z
Z
Z
Z
Z
Z
Z
L
Parallel
H
L
L
X
X
X
L
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
I
0
Load
Shift
H
L
H
H
L
L
L
D
0
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
1
Right
H
L
H
H
H
L
L
D
1
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
1
Sign
H
L
H
L
X
L
L
O
7
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
1
Extend
Hold
H
H
X
X
X
L
L
NC
NC
NC
NC
NC
NC
NC
NC
NC
When the OE input is HIGH all I O
n
terminals are at the high impedance state sequential operation or clearing of the register is not affected
Note 1
I
7
I
0
e
The level of the steady-state input at the respective I O terminal is loaded into the flip-flop while the flip-flop outputs (except Q
0
) are isolated from
the I O terminal
Note 2
D
0
D
1
e
The level of the steady-state inputs to the serial multiplexer input
Note 3
O
7
O
0
e
The level of the respective Q
n
flip-flop prior to the last Clock LOW-to-HIGH transition
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
Z
e
High Impedance Output State
L
e
LOW-to-HIGH Transition
NC
e
No Change
3
Logic Diagram
TL F 9516 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
4
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10% V
CC
2 5
I
OH
e b
1 mA (Q
0
I O
n
)
Voltage
54F 10% V
CC
2 4
I
OH
e b
3 mA (I O
n
)
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA (Q
0
I O
n
)
74F 10% V
CC
2 4
I
OH
e b
3 mA (I O
n
)
74F 5% V
CC
2 7
I
OH
e b
1 mA (Q
0
I O
n
)
74F 5% V
CC
2 7
I
OH
e b
3 mA (I O
n
)
V
OL
Output LOW
54F 10% V
CC
0 5
I
OL
e
20 mA (Q
0
I O
n
)
Voltage
74F 10% V
CC
0 5
V
Min
I
OL
e
20 mA (Q
0
)
74F 10% V
CC
0 5
I
OL
e
24 mA ( I O
n
)
I
IH
Input HIGH
54F
20 0
m
A
Max
V
IN
e
2 7V
Current
74F
5 0
I
BVI
Input HIGH Current
54F
100
m
A
Max
V
IN
e
7 0V (Non-I O Inputs)
Breakdown Test
74F
7 0
I
BVIT
Input HIGH Current
54F
1 0
mA
Max
V
IN
e
5 5V (I O
n
)
Breakdown Test (I O)
74F
0 5
I
CEX
Output HIGH
54F
250
m
A
Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4 75
V
0 0
I
ID
e
1 9 mA
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3 75
m
A
0 0
V
IOD
e
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V (RE S P D
n
CP MR OE)
b
1 2
mA
Max
V
IN
e
0 5V (S)
b
1 8
mA
Max
V
IN
e
0 5V (SE)
I
IH
a
Output Leakage Current
70
m
A
Max
V
I O
e
2 7V (I O
n
)
I
OZH
I
IL
a
Output Leakage Current
b
650
m
A
Max
V
I O
e
0 5V (I O
n
)
I
OZL
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V
I
ZZ
Bus Drainage Test
500
m
A
0 0V
V
OUT
e
5 25V
I
CC
Power Supply Current
60
90
mA
Max
5
AC Electrical Characteristics
74F
54F
74F
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Symbol
Parameter
V
CC
e a
5 0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
max
Maximum Clock Frequency
70
90
50
70
MHz
t
PLH
Propagation Delay
3 5
7 0
7 5
3 5
9 5
3 5
8 5
t
PHL
CP to I O
n
5 0
8 5
11 0
3 5
10 0
5 0
12 0
ns
t
PLH
Propagation Delay
3 5
7 0
9 0
3 5
11 0
3 5
10 0
t
PHL
CP to Q
0
3 5
7 0
8 0
3 5
10 0
3 5
9 0
t
PHL
Propagation Delay
6 0
10 0
13 0
6 0
15 0
6 0
14 0
ns
MR to I O
n
t
PHL
Propagation Delay
5 5
7 5
12 0
5 5
14 0
5 5
13 0
ns
MR to Q
0
t
PZH
Output Enable Time
3 0
6 5
9 0
3 0
12 5
3 0
10 0
t
PZL
OE to I O
n
4 0
8 5
11 0
4 0
14 5
4 0
12 0
ns
t
PHZ
Output Disable Time
2 0
4 5
6 0
2 0
8 0
2 0
7 0
t
PLZ
OE to I O
n
2 0
5 0
7 0
2 0
10 0
2 0
8 0
t
PZH
Output Enable Time
4 5
8 0
10 5
4 5
13 5
4 5
11 5
t
PZL
S P to I O
n
5 5
10 0
14 0
5 5
17 0
5 5
15 0
ns
t
PHZ
Output Disable Time
5 0
9 0
11 5
5 0
16 5
5 0
12 5
t
PLZ
S P to I O
n
6 0
12 0
15 5
6 0
19 5
6 0
16 5
AC Operating Requirements
74F
54F
74F
Symbol
Parameter
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Units
V
CC
e a
5 0V
Min
Max
Min
Max
Min
Max
t
s
(H)
Setup Time HIGH or LOW
6 0
14 0
7 0
ns
t
s
(L)
RE to CP
14 0
18 0
16 0
t
h
(H)
Hold Time HIGH or LOW
0
0
0
ns
t
h
(L)
RE to CP
0
0
0
t
s
(H)
Setup Time HIGH or LOW
6 5
8 5
7 5
ns
t
s
(L)
D
0
D
1
or I O
n
to CP
6 5
8 5
7 5
t
h
(H)
Hold Time HIGH or LOW
2 0
3 0
3 0
ns
t
h
(L)
D
0
D
1
or I O
n
to CP
2 0
3 0
3 0
t
s
(H)
Setup Time HIGH or LOW
7 0
9 0
8 0
ns
t
s
(L)
SE to CP
2 5
11 0
3 5
t
h
(H)
Hold Time HIGH or LOW
2 0
2 0
2 0
ns
t
h
(L)
SE to CP
0 0
1 0
0 0
t
s
(H)
Setup Time HIGH or LOW
11 0
13 0
12 0
ns
t
s
(L)
S P to CP
13 5
21 0
15 5
t
s
(H)
Setup Time HIGH or LOW
6 5
8 5
7 5
ns
t
s
(L)
S to CP
9 0
11 0
10 0
t
h
(H)
Hold Time HIGH or LOW
0
1 0
0
ns
t
h
(L)
S or S P to CP
0
0
0
t
w
(H)
CP Pulse Width HIGH or LOW
7 0
8 0
7 0
ns
t
w
(L)
t
w
(L)
MR Pulse Width LOW
5 5
7 5
6 5
t
rec
Recovery Time
8 0
12 0
8 0
ns
MR to CP
6
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
322
S
C
X
Temperature Range Family
Special Variations
74F
e
Commercial
QB
e
Military grade device with
54F
e
Military
environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13 reel
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0 C to
a
70 C)
D
e
Ceramic DIP
M
e
Military (
b
55 C to
a
125 C)
F
e
Flatpak
SJ
e
Small Outline SOIC EIAJ
L
e
Leadless Chip Carrier (LCC)
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
7
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
8
Physical Dimensions
inches (millimeters) (Continued)
20-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ)
NS Package Number M20D
20-Lead (0 300 Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
9
54F74F322
Octal
SerialParallel
Register
with
Sign
Extend
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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Corporation
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