TL F 9567
54F74F574
Octal
D-Type
Flip-Flop
with
TRI-STATE
Outputs
May 1995
54F 74F574
Octal D-Type Flip-Flop with TRI-STATE
Outputs
General Description
The 'F574 is a high-speed low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Out-
put Enable (OE) The information presented to the D inputs
is stored in the flip-flops on the LOW-to-HIGH Clock (CP)
transition
This device is functionally identical to the 'F374 except for
the pinouts
Features
Y
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Y
Useful as input or output port for microprocessors
Y
Functionally identical to 'F374
Y
TRI-STATE outputs for bus-oriented applications
Commercial
Military
Package
Package Description
Number
74F574PC
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
54F574DM (Note 2)
J20A
20-Lead Ceramic Dual-In-Line
74F574SC (Note 1)
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
74F574SJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
54F574FM (Note 2)
W20A
20-Lead Cerpack
54F574LM (Note 2)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
TL F 9567 1
IEEE IEC
TL F 9567 4
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
D
0
D
7
Data Inputs
1 0 1 0
20 mA
b
0 6 mA
CP
Clock Pulse Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
OE
TRI-STATE Output Enable Input (Active LOW)
1 0 1 0
20 mA
b
0 6 mA
O
0
O
7
TRI-STATE Outputs
150 40 (33 3)
b
3 mA 24 mA (20 mA)
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
TL F 9567 2
Pin Assignment
for LCC
TL F 9567 3
Functional Description
The 'F574 consists of eight edge-triggered flip-flops with in-
dividual D-type inputs and TRI-STATE true outputs The
buffered clock and buffered Output Enable are common to
all flip-flops The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times re-
quirements on the LOW-to-HIGH Clock (CP) transition With
the Output Enable (OE) LOW the contents of the eight flip-
flops are available at the outputs When OE is HIGH the
outputs go to the high impedance state Operation of the
OE input does not affect the state of the flip-flops
Function Table
Inputs
Internal
Outputs
Function
OE
CP
D
Q
O
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L L
L
Z
Load
H
L H
H
Z
Load
L
L L
L
L
Data Available
L
L H
H
H
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL F 9567 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10% V
CC
2 5
I
OH
e b
1 mA
Voltage
54F 10% V
CC
2 4
I
OH
e b
3 mA
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA
74F 10% V
CC
2 4
I
OH
e b
3 mA
74F 5% V
CC
2 7
I
OH
e b
1 mA
74F 5% V
CC
2 7
I
OH
e b
3 mA
V
OL
Output LOW
54F 10% V
CC
0 5
V
Min
I
OL
e
20 mA
Voltage
74F 10% V
CC
0 5
I
OL
e
24 mA
I
IH
Input HIGH
54F
20 0
m
A
Max
V
IN
e
2 7V
Current
74F
5 0
I
BVI
Input HIGH Current
54F
100
m
A
Max
V
IN
e
7 0V
Breakdown Test
74F
7 0
I
CEX
Output HIGH
54F
250
m
A
Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4 75
V
0 0
I
ID
e
1 9 mA
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3 75
m
A
0 0
V
IOD
e
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V
I
OZH
Output Leakage Current
50
m
A
Max
V
OUT
e
2 7V
I
OZL
Output Leakage Current
b
50
m
A
Max
V
OUT
e
0 5V
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V
I
ZZ
Bus Drainage Test
500
m
A
0 0V
V
OUT
e
5 25V
I
CCZ
Power Supply Current
55
86
mA
Max
V
O
e
HIGH Z
3
AC Electrical Characteristics
74F
54F
74F
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Symbol
Parameter
V
CC
e a
5 0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
max
Maximum Clock Frequency
100
60
70
MHz
t
PLH
Propagation Delay
2 5
5 3
8 5
2 5
9 5
2 5
8 5
ns
t
PHL
CP to O
n
2 5
5 3
8 5
2 5
9 5
2 5
8 5
t
PZH
Output Enable Time
3 0
5 5
9 0
2 5
10 5
2 5
10 0
t
PZL
3 0
6 0
9 0
2 5
10 5
2 5
10 0
ns
t
PHZ
Output Disable Time
1 5
3 3
5 5
1 5
7 0
1 5
6 5
t
PLZ
1 5
2 8
5 5
1 5
7 0
1 5
6 5
AC Operating Requirements
74F
54F
74F
Symbol
Parameter
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Units
V
CC
e a
5 0V
Min
Max
Min
Max
Min
Max
t
s
(H)
Set-up Time HIGH or LOW
2 5
3 0
2 5
t
s
(L)
D
n
to CP
2 0
2 5
2 0
ns
t
h
(H)
Hold Time HIGH or LOW
2 0
2 0
2 0
t
h
(L)
D
n
to CP
2 0
2 0
2 0
t
w
(H)
CP Pulse Width
5 0
5 0
5 0
ns
t
w
(L)
HIGH or LOW
5 0
5 0
5 0
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
574
S
C
X
Temperature Range Family
Special Variations
74F
e
Commercial
QB
e
Military grade device with
54F
e
Military
environmental and burn-in
processing
Device Type
Temperature Range
Package Code
C
e
Commercial (0 C to
a
70 C)
P
e
Plastic DIP
M
e
Military (
b
55 C to
a
125 C)
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline JEDEC
SJ
e
Small Outline SOIC EIAJ
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S)
NS Package Number M20B
6
Physical Dimensions
inches (millimeters) (Continued)
20-Lead (0 300 Wide) Molded Small Outline Package EIAJ
NS Package Number M20D
20-Lead (0 300 Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
7
54F74F574
Octal
D-Type
Flip-Flop
with
TRI-STATE
Outputs
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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