TL F 9821
DM54LS181DM74LS181
4-Bit
Arithmetic
Logic
Unit
June 1992
DM54LS181 DM74LS181
4-Bit Arithmetic Logic Unit
General Description
The 'LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations
Features
Y
Provides 16 arithmetic operations add subtract com-
pare double plus twelve other arithmetic operations
Y
Provides all 16 logic operations of two variables exclu-
sive-OR compare AND NAND OR NOR plus ten
other logic operations
Y
Full lookahead for high speed arithmetic operation on
long words
Connection Diagram
Dual-In-Line Package
TL F 9821 1
Order Number DM54LS181J DM54LS181W or DM74LS181N
See NS Package Number J24A N24A or W24C
Pin Names
Description
A0 A3
Operand Inputs (Active LOW)
B0 B3
Operand Inputs (Active LOW)
S0 S3
Function Select Inputs
M
Mode Control Input
C
n
Carry Input
F0 F3
Function Outputs (Active LOW)
A
e
B
Comparator Output
G
Carry Generate Output (Active LOW)
P
Carry Propagate Output (Active LOW)
C
na4
Carry Output
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Note)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54LS181
DM74LS181
Units
Min
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 7
0 8
V
I
OH
High Level Output Current
b
0 4
b
0 4
mA
I
OL
Low Level Output Current
4
8
mA
T
A
Free Air Operating Temperature
b
55
125
0
70
C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
18 mA
b
1 5
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
DM54
2 5
V
Voltage
V
IL
e
Max
DM74
2 7
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
DM54
0 4
V
Voltage
V
IH
e
Min
DM74
0 35
0 5
I
OL
e
4 mA V
CC
e
Min
DM74
0 25
0 4
I
I
Input Current
Max
V
CC
e
Max V
I
e
7V
M input
0 1
Input Voltage
V
I
e
10V (DM54)
A
n
B
n
0 3
mA
S
n
0 4
C
n
0 5
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 7V
M input
20
A
n
B
n
60
m
A
S
n
80
C
n
100
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 4V
M input
b
0 4
A
n
B
n
b
1 2
mA
S
n
b
1 6
C
n
b
2 0
I
OS
Short Circuit
V
CC
e
Max
b
20
b
100
mA
Output Current
(Note 2)
I
CC
Supply Current
V
CC
e
Max B
n
C
n
e
GND
DM54
35
mA
S
n
M A
n
e
4 5V
DM74
37
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
2
Switching Characteristics
DM54 DM74LS
Symbol
Parameter
Conditions
C
L
e
15 pF
Units
Min
Max
t
PLH
Propagation Delay
M
e
GND
27
ns
t
PHL
C
n
to C
na4
20
t
PLH
Propagation Delay
M
e
GND
26
ns
t
PHL
C
n
to F
20
t
PLH
Propagation Delay
M S
1
S
2
e
GND
29
ns
t
PHL
A or B to G (Sum)
S
1
S
3
e
4 5V
23
t
PLH
Propagation Delay
M S
0
S
3
e
GND
32
ns
t
PHL
A or B to G (Diff)
S
1
S
2
e
4 5V
26
t
PLH
Propagation Delay
M S
1
S
2
e
GND
30
ns
t
PHL
A or B to P (Sum)
S
0
S
3
e
4 5V
30
t
PLH
Propagation Delay
M S
0
S
3
e
GND
30
ns
t
PHL
A or B to P (Diff)
S
1
S
2
e
4 5V
33
t
PLH
Propagation Delay
M S
1
S
2
e
GND
32
ns
t
PHL
A
i
or B
i
to F
i
(Sum)
S
0
S
3
e
4 5V
25
t
PLH
Propagation Delay
M S
0
S
3
e
GND
32
ns
t
PHL
A
i
or B
i
to F
i
(Diff)
S
1
S
2
e
4 5V
33
t
PLH
Propagation Delay
M
e
4 5V
33
ns
t
PHL
A or B to F (Logic)
29
t
PLH
Propagation Delay
M S
1
S
2
e
GND
38
ns
t
PHL
A or B to C
na4
(Sum)
S
0
S
3
e
4 5V
38
t
PLH
Propagation Delay
M S
0
S
3
e
GND
41
ns
t
PHL
A or B to C
na4
(Diff)
S
1
S
2
e
4 5V
41
t
PLH
Propagation Delay
M S
0
S
3
e
GND
50
ns
t
PHL
A or B to A
e
B
S
1
S
2
e
4 5V
62
R
L
e
2 kX to 5 0V
3
Sum Mode Test Table I
Function Inputs
S0
e
S3
e
4 5V S1
e
S2
e
M
e
0V
Input
Other Input
Other Data Inputs
Output
Symbol
Under
Same Bit
Under
Test
Apply
Apply
Apply
Apply
Test
4 5V
GND
4 5V
GND
t
PLH
A
i
B
i
None
Remaining
C
n
F
i
t
PHL
A and B
t
PLH
B
i
A
i
None
Remaining
C
n
F
i
t
PHL
A and B
t
PLH
A
B
None
None
Remaining
P
t
PHL
A and B C
n
t
PLH
B
A
None
None
Remaining
P
t
PHL
A and B C
n
t
PLH
A
None
B
Remaining
Remaining
G
t
PHL
B
A C
n
t
PLH
B
None
A
Remaining
Remaining
G
t
PHL
B
A C
n
t
PLH
A
None
B
Remaining
Remaining
C
na4
t
PHL
B
A C
n
t
PLH
B
None
A
Remaining
Remaining
C
na4
t
PHL
B
A C
n
t
PLH
C
n
None
None
All
All
Any F
t
PHL
A
B
or C
na4
Diff Mode Test Table II
Function Inputs
S1
e
S2
e
4 5V S0
e
S3
e
M
e
0V
Input
Other Input
Other Data Inputs
Output
Symbol
Under
Same Bit
Under
Test
Apply
Apply
Apply
Apply
Test
4 5V
GND
4 5V
GND
t
PLH
A
None
B
Remaining
Remaining
F
i
t
PHL
A
B C
n
t
PLH
B
A
None
Remaining
Remaining
F
i
t
PHL
A
B C
n
t
PLH
A
None
B
None
Remaining
P
t
PHL
A and B C
n
t
PLH
B
A
None
None
Remaining
P
t
PHL
A and B C
n
t
PLH
A
B
None
None
Remaining
G
t
PHL
A and B C
n
t
PLH
B
None
A
None
Remaining
G
t
PHL
A and B C
n
t
PLH
A
None
B
Remaining
Remaining
A
e
B
t
PHL
A
B C
n
t
PLH
B
A
None
Remaining
Remaining
A
e
B
t
PHL
A
B C
n
t
PLH
A
B
None
None
Remaining
C
na4
t
PHL
A and B C
n
t
PLH
B
None
A
None
Remaining
C
na4
t
PHL
A and B C
n
t
PLH
C
n
None
None
All
None
C
na4
t
PHL
A and B
4
Logic Mode Test Table III
Function Inputs
S1
e
S2
e
M
e
4 5V S0
e
S3
e
0V
Input
Other Input
Other Data Inputs
Output
Symbol
Under
Same Bit
Under
Test
Apply
Apply
Apply
Apply
Test
4 5V
GND
4 5V
GND
t
PLH
A
B
None
None
Remaining
Any F
t
PHL
A and B C
n
t
PLH
B
A
None
None
Remaining
Any F
t
PHL
A and B C
n
Functional Description
The 'LS181 is a 4-bit high speed parallel Arithmetic Logic
Unit (ALU) Controlled by the four Function Select inputs
(S0 S3) and the Mode Control input (M) it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands The
Function Table lists these operations
When the Mode Control input (M) is HIGH all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed When the Mode Control input
is LOW the carries are enabled and the device performs
arithmetic operations on the two 4-bit words The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the C
na4
output
or for carry lookahead between packages using the signals
P (Carry Propagate) and G (Carry Generate) In the ADD
mode P indicates that F is 15 or more while G indicates
that F is 16 or more In the SUBTRACT mode P indicates
that F is zero or less while G indicates that F is less than
zero P and G are not affected by carry in When speed
requirements are not stringent it can be used in a simple
ripple carry mode by connecting the Carry output (C
na4
)
signal to the Carry input (C
n
) of the next unit For high speed
operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit One carry lookahead pack-
age is required for each group of four 'LS181 devices Carry
lookahead can be provided at various levels and offers high
speed capability over extremely long word lengths
The A
e
B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logic equiv-
alence over four bits when the unit is in the subtract mode
The A
e
B output is open-collector and can be wired-AND
with other A
e
B outputs to give a comparison for more
than four bits The A
e
B signal can also be used with the
C
na4
signal to indicate A
l
B and A
k
B
The Function Table lists the arithmetic operations that are
performed without a carry in An incoming carry adds a one
to each operation Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied Be-
cause subtraction is actually performed by complementary
addition (1s complement) a carry out means borrow thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow As indicated this de-
vice can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs For either case the table lists the oper-
ations that are performed to the operands labeled inside the
logic symbol
Function Table
Mode Select
Active LOW Operands
Active HIGH Operands
Inputs
F
n
Outputs
F
n
Outputs
Logic
Arithmetic
Logic
Arithmetic
S3
S2
S1
S0
(M
e
H)
(M
e
L) (C
n
e
L)
(M
e
H)
(M
e
L) (C
n
e
H)
L
L
L
L
A
A minus 1
A
A
L
L
L
H
AB
AB minus 1
A
a
B
A
a
B
L
L
H
L
A
a
B
AB minus 1
AB
A
a
B
L
L
H
H
Logic 1
minus 1
Logic 0
minus 1
L
H
L
L
A
a
B
A plus (A
a
B)
AB
A plus AB
L
H
L
H
B
AB plus (A
a
B)
B
(A
a
B) plus AB
L
H
H
L
A
Z
B
A minus B minus 1
A
Z
B
A minus B minus 1
L
H
H
H
A
a
B
A
a
B
AB
AB minus 1
H
L
L
L
AB
A plus (A
a
B)
A
a
B
A plus AB
H
L
L
H
A
Z
B
A plus B
A
Z
B
A plus B
H
L
H
L
B
AB plus (A
a
B)
B
(A
a
B) plus AB
H
L
H
H
A
a
B
A
a
B
AB
AB minus 1
H
H
L
L
Logic 0
A plus A
Logic 1
A plus A
H
H
L
H
AB
AB plus A
A
a
B
(A
a
B) plus A
H
H
H
L
AB
AB minus A
A
a
B
(A
a
B) plus A
H
H
H
H
A
A
A
A minus 1
Each bit is shifted to the next most significant position
Arithmetic operations expressed in 2s complement notation
5
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