TL F 12157
74LVX163
Low
Voltage
Synchronous
Binary
Counter
with
Synchronous
Clear
December 1996
74LVX163
Low Voltage Synchronous Binary Counter with
Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter
This device is synchronously presettable for application in
programmable dividers and has two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
multistage counters The CLK input is active on the rising
edge Both PE and CLR inputs are active on low logic lev-
els Presetting is synchronous to rising edge of CLK and the
Clear function of the LVX163 is synchronous to CLK Two
enable inputs (ENP and ENT) and Carry Output are provid-
ed to enable easy cascading of counters which facilitates
easy implementation of n-bit counters without using external
gates
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems
Features
Y
Input voltage level translation from 5V to 3V
Y
Ideal for low power low noise 3 3V applications
Y
Available in SOIC JEDEC
SOIC EIAJ
and TSSOP
packages
Y
Guaranteed simultaneous switching noise and dynamic
threshold performance
Logic Symbols
TL F 12157 1
IEEE IEC
TL F 12157 2
Connection Diagram
Pin Assignment for
TSSOP and SOIC
TL F 12157 3
SOIC JEDEC
SOIC EIAJ
TSSOP
Order Number
74LVX163M
74LVX163SJ
74LVX163MTC
74LVX163MX
74LVX163SJX
74LVX163MTCX
See NS Package
M16A
M16D
MTC16
Number
Pin
Description
Names
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
Synchronous Master Reset Input
P
0
P
3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q
0
Q
3
Flip-Flop Outputs
TC
Terminal Count Output
C1996 National Semiconductor Corporation
RRD-B30M17 Printed in U S A
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Functional Description
The LVX163 counts in modulo-16 binary sequence From
state 15 (HHHH) it increments to state 0 (LLLL) The clock
inputs of all flip-flops are driven in parallel through a clock
buffer Thus all changes of the Q outputs occur as a result
of and synchronous with the LOW-to-HIGH transition of
the CP input signal The circuits have four fundamental
modes of operation in order of precedence synchronous
reset parallel load count-up and hold Four control inputs
Synchronous Reset (MR) Parallel Enable (PE) Count En-
able Parallel (CEP) and Count Enable Trickle (CET)
deter-
mine the mode of operation as shown in the Mode Select
Table A LOW signal on MR overrides counting and parallel
loading and allows all outputs to go LOW on the next rising
edge of CP A LOW signal on PE overrides counting and
allows information on the Parallel Data (P
n
) inputs to be
loaded into the flip-flops on the next rising edge of CP With
PE and MR HIGH CEP and CET permit counting when both
are HIGH Conversely a LOW signal on either CEP or CET
inhibits counting
The LVX163 uses D-type edge-triggered flip-flops and
changing the MR PE CEP and CET inputs when the CP is
in either state does not cause errors provided that the rec-
ommended setup and hold times with respect to the rising
edge of CP are observed
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15 To implement synchronous multi-
stage counters the TC outputs can be used with the CEP
and CET inputs in two different ways
Figure 1 shows the connections for simple ripple carry in
which the clock period must be longer than the CP to TC
delay of the first stage plus the cumulative CET to TC de-
lays of the intermediate stages plus the CET to CP setup
time of the last stage This total delay plus setup time sets
the upper limit on clock frequency For faster clock rates
the carry lookahead connections shown in
Figure 2 are rec-
ommended In this scheme the ripple delay through the in-
termediate stages commences with the same clock that
causes the first stage to tick over from max to min in the Up
mode or min to max in the Down mode to start its final
cycle Since this final cycle takes 16 clocks to complete
there is plenty of time for the ripple to progress through the
intermediate stages The critical timing that limits the clock
period is the CP to TC delay of the first stage plus the CEP
to CP setup time of the last stage The TC output is subject
to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops registers or counters When the
Output Enable (OE) is LOW the parallel data outputs O
0
O
3
are active and follow the flip-flop Q outputs A HIGH
signal on OE forces O
0
O
3
to the High Z state but does not
prevent counting loading or resetting
Logic Equations Count Enable
e
CEP
CET
PE
TC
e
Q
0
Q
1
Q
2
Q
3
CET
Mode Select Table
MR
PE
CET
CEP
Action on the Rising
Clock Edge (
L )
L
X
X
X
Reset (Clear)
H
L
X
X
Load (P
n
x
Q
n
)
H
H
H
H
Count (Increment)
H
H
L
X
No Change (Hold)
H
H
X
L
No Change (Hold)
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
State Diagram
TL F 12157 4
TL F 12157 5
FIGURE 1
TL F 12157 6
FIGURE 2
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Block Diagram
TLF12157
7
Please
note
that
this
diagram
is
provided
only
for
the
understanding
of
logic
operations
and
should
not
be
used
to
estimate
propagation
delays
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3
Absolute Maximum Ratings
(Note)
Supply Voltage (V
CC
)
b
0 5V to
a
7 0V
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
b
20 mA
DC Input Voltage (V
I
)
b
0 5V to 7V
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
b
20 mA
V
O
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
O
)
b
0 5V to V
CC
a
0 5V
DC Output Source
or Sink Current (I
O
)
g
25 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
g
50 mA
Storage Temperature (T
STG
)
b
65 C to
a
150 C
Power Dissipation
180 mW
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating
Conditions
Supply Voltage (V
CC
)
2 0V to 3 6V
Input Voltage (V
I
)
0V to 5 5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
b
40 C to
a
85 C
Input Rise and Fall Time (D
t
D
v
)
0 ns V to 100 ns V
DC Electrical Characteristics
Symbol
Parameter
V
CC
74LVX163
74LVX163
Units
Conditions
T
A
e a
25 C
T
A
e
b
40 C to
a
85 C
Min
Typ
Max
Min
Max
V
IH
High Level
2 0
1 5
1 5
Input
3 0
2 0
2 0
V
Voltage
3 6
2 4
2 4
V
IL
Low Level
2 0
0 5
0 5
Input
3 0
0 8
0 8
V
Voltage
3 6
0 8
0 8
V
OH
High Level
2 0
1 9
2 0
1 9
V
IN
e
V
IL
or V
IH
I
OH
e b
50 mA
Output
3 0
2 9
3 0
2 9
V
I
OH
e b
50 mA
Voltage
3 0
2 58
2 48
I
OH
e b
4 mA
V
OL
Low Level
2 0
0 0
0 1
0 1
V
IN
e
V
IL
or V
IH
I
OL
e
50 mA
Output
3 0
0 0
0 1
0 1
V
I
OL
e
50 mA
Voltage
3 0
0 36
0 44
I
OL
e
4 mA
I
IN
Input
3 6
g
0 1
g
1 0
m
A
V
IN
e
5 5V or GND
Leakage
Current
I
CC
Quiescent
3 6
2 0
20 0
m
A
V
IN
e
V
CC
or GND
Supply
Current
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Noise Characteristics
V
CC
(V)
LVX163
Symbol
Parameter
T
A
e
25 C
Units
C
L
(pF)
Typ
Limits
V
OLP
Quiet Output Maximum
3 3
0 2
0 5
V
50
Dynamic V
OL
V
OLV
Quiet Output Minimum
3 3
b
0 2
b
0 5
V
50
Dynamic V
OL
V
IHD
Minimum High Level
3 3
2 0
V
50
Dynamic Input Voltage
V
ILD
Maximum Low Level
3 3
0 8
V
50
Dynamic Input Voltage
Parameter guaranteed by design
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
LVX163
LVX163
Units
Conditions
T
A
e
25 C
T
A
e b
40 C
to
a
85 C
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
2 7
9 0
14 0
1 0
16 0
ns
C
L
e
15 pF
t
PHL
Time (CP Q
n
)
11 3
17 0
1 0
19 0
C
L
e
50 pF
3 3
g
0 3
8 3
12 8
1 0
15 0
ns
C
L
e
15 pF
10 8
16 3
1 0
18 5
C
L
e
50 pF
t
PLH
Propagation Delay
2 7
9 5
14 3
1 0
16 7
ns
C
L
e
15 pF
t
PHL
Time (CP TC Count)
12 5
18 5
1 0
20 5
C
L
e
50 pF
3 3
g
0 3
8 7
13 6
1 0
16 0
ns
C
L
e
15 pF
11 2
17 1
1 0
19 5
C
L
e
50 pF
t
PLH
Propagation Delay
2 7
11 4
18 0
1 0
21 0
ns
C
L
e
15 pF
t
PHL
Time (CP TC Load)
14 0
21 0
1 0
24 0
C
L
e
50 pF
3 3
g
0 3
11 0
17 2
1 0
20 0
ns
C
L
e
15 pF
13 5
20 7
1 0
23 5
C
L
e
50 pF
t
PLH
Propagation Delay
2 7
8 6
13 5
1 0
15 0
ns
C
L
e
15 pF
t
PHL
Time (CET TC)
11 0
16 5
1 0
18 5
C
L
e
50 pF
3 3
g
0 3
7 5
12 3
1 0
14 5
ns
C
L
e
15 pF
10 5
15 8
1 0
18 0
C
L
e
50 pF
f
max
Maximum Clock
2 7
75
115
65
MHz
C
L
e
15 pF
Frequency
50
80
45
C
L
e
50 pF
3 3
g
0 3
80
130
70
MHz
C
L
e
15 pF
55
85
50
C
L
e
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
e
Open
C
PD
Power Dissipation
23
pF
(Note 1)
Capacitance
Note 1
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average
operating current can be obtained by the equation I
CC
(opr)
e
C
PD
V
CC
f
IN
a
I
CC
When the outputs drive a capacitive load total current consumption is the sum of C
PD
and DI
CC
which is obtained from the following formula
D
I
CC
e
F
CP
V
CC
C
QO
2
a
C
Q1
4
a
C
Q2
8
a
C
Q3
16
a
C
TC
16
J
C
Q0
C
Q3
and C
TC
are the capacitances at Q0Q3 and TC respectively F
CP
is the input frequency of the CP
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