TL F 9576
93L00
4-Bit
Universal
Shift
Register
June 1989
93L00
4-Bit Universal Shift Register
General Description
The 93L00 is a 4-bit universal shift register As a high speed
multifunctional sequential logic block it is useful in a wide
variety of register and counter applications It may be used
in serial-serial shift left shift right serial-parallel parallel-
serial and parallel-parallel data register transfers
Features
Y
Asynchronous master reset
Y
J K inputs to first stage
Connection Diagram
Dual-In-Line Package
TL F 9576 1
Order Number 93L00DMQB or 93L00FMQB
See NS Package Number J16A or W16A
Logic Symbol
TL F 9576 2
V
CC
e
Pin 16
GND
e
Pin 8
Pin Names
Description
PE
Parallel Enable Input (Active LOW)
P0 P3
Parallel Inputs
J
First Stage J Input (Active HIGH)
K
First Stage K Input (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
MR
Master Reset Input
Q0 Q3
Parallel Outputs
Q3
Complementary Last Stage Output
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL
b
65 C to
a
125 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
93L00 (MIL)
Units
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Voltage
b
0 4
mA
I
OL
Low Level Output Current
4 8
mA
T
A
Free Air Operating Temperature
b
55
125
C
t
s
(H)
Setup Time HIGH or LOW
60
ns
t
s
(L)
J K and P0 P3 to CP
60
t
h
(H)
Hold Time HIGH or LOW
0
ns
t
h
(L)
J K and P0 P3 to CP
0
t
s
(H)
Setup Time HIGH or LOW
68
ns
t
s
(L)
PE to CP
68
t
h
(H)
Hold Time HIGH or LOW
0
ns
t
h
(L)
PE to CP
0
t
w
(H)
CP Pulse Width
38
ns
t
w
(L)
HIGH or LOW
38
t
w
(L)
MR Pulse Width LOW
53
ns
t
rec
Recovery Time MR to CP
70
ns
2
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
10 mA
b
1 5
V
V
OH
High Level Output Voltage
V
CC
e
Min I
OH
e
Max
2 4
3 4
V
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output Voltage
V
CC
e
Min I
OL
e
Max
0 3
V
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 4V
Inputs
20
CP
40
m
A
PE
46
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 3V
Inputs
b
400
CP
b
800
m
A
PE
b
920
I
OS
Short Circuit
V
CC
e
Max
b
2 5
b
25
mA
Output Current
(Note 2)
I
CC
Supply Current
V
CC
e
Max
23
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 1 for waveforms and load configurations)
93L
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
f
max
Maximum Shift Frequency
10
MHz
t
PLH
Propagation Delay
35
ns
t
PHL
CP to Q
n
51
t
PHL
Propagation Delay MR to Q
n
60
ns
3
Functional Description
The Logic Diagrams and Truth Table indicate the functional
characteristics of the 93L00 4-bit shift register The device is
useful in a wide variety of shifting counting and storage
applications It performs serial parallel serial-to-parallel or
parallel-to-serial data transfers
The 93L00 has two primary modes of operation shift right
(Q0
x
Q1) and parallel load which are controlled by the
state of the Parallel Enable (PE) input When the PE input is
HIGH serial data enters the first flip-flop Q0 via the J and K
inputs
and
is
shifted
one
bit
in
the
direction
Q0
x
Q1
x
Q2
x
Q3
following
each
LOW-to-HIGH
clock transition The JK inputs provide the flexibility of the
JK type input for special applications and the simple D-type
input for general applications by tying the two pins together
When the PE input is LOW the 93L00 appears as four com-
mon clocked D flip-flops The data on the parallel inputs
P0 P3 is transferred to the respective Q0 Q3 outputs fol-
lowing the LOW-to-HIGH clock transition Shift left opera-
tion (Q3
x
Q2) can be achieved by tying the Qn outputs to
the Pn
b
1 inputs and holding the PE input LOW
All serial and parallel data transfers are synchronous occur-
ing after each LOW-to-HIGH clock transition Since the
93L00 utilizes edge triggering there is no restriction on the
activity of the J K Pn and PE inputs for logic operation
ex-
cept for the setup and release time requirements A LOW on
the asynchronous Master Reset (MR) input sets all Q out-
puts LOW independent of any other input condition
Truth Table
Operating
Inputs (MR
e
H)
Outputs
t
na1
Mode
PE
J
K
P0
P1
P2
P3
Q0
Q1
Q2
Q3
Q3
H
L
L
X
X
X
X
L
Q0
Q1
Q2
Q2
Shift Mode
H
L
H
X
X
X
X
Q0
Q0
Q1
Q2
Q2
H
H
L
X
X
X
X
Q0
Q0
Q1
Q2
Q2
H
H
H
X
X
X
X
H
Q0
Q1
Q2
Q2
Parallel
L
X
X
L
L
L
L
L
L
L
L
H
Entry Mode
L
X
X
H
H
H
H
H
H
H
H
L
t
n
a
1
e
Indicates state after next LOW-to-HIGH clock transition
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
4
Logic Diagram
TLF9576
3
5
6
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L00DMQB
NS Package Number J16A
7
93L00
4-Bit
Universal
Shift
Register
Physical Dimensions
inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 93L00FMQB
NS Package Number W16A
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into the body or (b) support or sustain life and whose
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failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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