TL F 10200
93L28
Dual
8-Bit
Shift
Register
June 1989
93L28
Dual 8-Bit Shift Register
General Description
The 93L28 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers The
multifunctional capability of this device is provided by sever-
al features 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources 2) the clock of each register may be
provided separately or together 3) both the true and com-
plementary outputs are provided from each 8-bit register
and both registers may be master cleared from a common
input
Features
Y
2-input multiplexer provided at data input of each
register
Y
Gated clock input circuitry
Y
Both true and complementary outputs provided from
last bit of each register
Y
Asynchronous master reset common to both registers
Connection Diagram
Dual-In-Line Package
TL F 10200 1
Order Number 93L28DMQB or 93L28FMQB
See NS Package Number J16A or W16A
Logic Symbol
TL F 10200 2
V
CC
e
Pin 16
GND
e
Pin 8
Pin
Description
Names
S
Data Select Input
D0 D1
Data Inputs
CP
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
MR
Master Reset Input (Active LOW)
Q7
Last Stage Output
Q7
Complementary Output
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL
b
55 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
93L28 (MIL)
Units
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Current
b
400
m
A
I
OL
Low Level Output Current
4 8
mA
T
A
Free Air Operating Temperature
b
55
125
C
t
s
(H)
Setup Time HIGH or LOW
30
ns
t
s
(L)
D
n
to CP
30
t
h
(H)
Hold Time HIGH or LOW
0
ns
t
h
(L)
D
n
to CP
0
t
w
(H)
Clock Pulse Width
55
ns
t
w
(L)
HIGH or LOW
55
t
w
(L)
MR Pulse Width with CP HIGH
60
ns
t
w
(L)
MR Pulse Width with CP LOW
70
ns
2
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
10 mA
b
1 5
V
V
OH
High Level Output Voltage
V
CC
e
Min I
OH
e
Max
2 4
V
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output Voltage
V
CC
e
Min I
OL
e
Max
0 3
V
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
HIGH Level
V
CC
e
Max V
I
e
2 4V
MR Dx
20
Input Current
CP (7 10)
30
m
A
S
40
CP Com
60
I
IL
LOW Level
V
CC
e
Max V
I
e
0 3V
MR Dx
b
400
Input Current
CP (7 10)
b
600
m
A
S
b
800
CP Com
b
1200
I
OS
Short Circuit
V
CC
e
Max
b
2 5
b
25
mA
Output Current
(Note 2)
I
CC
Supply Current
V
CC
e
Max
25 3
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 1 for test waveforms and output load)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
f
max
Maximum Shift Right Frequency
5 0
MHz
t
PLH
Propagation Delay
45
ns
t
PHL
CP to Q
7
or Q
7
80
t
PHL
Propagation Delay MR to Q
7
110
ns
3
Functional Description
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7) The clocking
of each register is controlled by the OR function of the sep-
arate and the common clock input Each register is com-
posed of eight clocked RS master slave flip-flops and a
number of gates The clock OR gate drives the eight clock
inputs of the flip-flops in parallel When the two clock inputs
(the separate and the common) to the OR gate are LOW
the slave latches are steady but data can enter the master
latches via the R and S input During the first LOW-to-HIGH
transition of either or both simultaneously of the two clock
inputs the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master then the now
trapped information in the master is transferred to the slave
When the transfer is complete both the master and the
slave are steady as long as either or both clock inputs re-
main HIGH During the HIGH-to-LOW transition of the last
remaining HIGH clock input the transfer path from master
to slave is inhibited first leaving the slave steady in its pres-
ent state The data inputs (R and S) are enabled so that new
data can enter the master Either of the clock inputs can be
used as clock inhibit inputs by applying a logic HIGH signal
Each 8-bit shift register has a 2-input multiplexer in front of
the serial data input The two data inputs D0 and D1 are
controlled by the data select input (S) following the Boolean
expression
Serial data in S
D
e
SD0
a
SD1
An asynchronous master reset is provided which when acti-
vated by a LOW logic level will clear all 16 stages indepen-
dently of any other input signal
Shift Select Table
Inputs
Output
S
D0
D1
Q7 (t
na8
)
L
L
X
L
L
H
X
H
H
X
L
L
H
X
H
H
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
n
a
8
e
Indicates state after eight clock pulse
Logic Diagram
TL F 10200 3
4
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L28DMQB
NS Package Number J16A
5
93L28
Dual
8-Bit
Shift
Register
Physical Dimensions
inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 93L28FMQB
NS Package Number W16A
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failure to perform when properly used in accordance
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with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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