ADC083000
High Performance, Low Power, 8-Bit, 3 GSPS A/D
Converter
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC083000 is a single, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 3.4 GSPS. Consuming
a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters up to Nyquist, pro-
ducing a high 7.0 ENOB with a 748 MHz input signal and a
3 GHz sample rate while providing a 10
-18
B.E.R. The
ADC083000 achieves a 3GSPS sampling rate by utilizing
both the rising and falling edge of a 1.5 GSPS input clock.
Output formatting is offset binary and the LVDS digital out-
puts are compliant with IEEE 1596.3-1996, with the excep-
tion of an adjustable common mode voltage between 0.8V
and 1.2V.
The ADC has a 1:4 demultiplexer that feeds four LVDS
buses and reduces the output data rate on each bus to a
quarter of the sampling rate. The ADC can be programmed
into the 1:2 Output Mode where the data is output on the Dc
and Dd channels at the rate of the input clock.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40C
T
A
+85C) temperature range.
Features
n
Internal Sample-and-Hold
n
Single +1.9V
0.1V Operation
n
Choice of SDR or DDR output clocking
n
1:2 or 1:4 Selectable Output Demux
n
Clock Phase Adjust for Multiple ADC Synchronization
n
Guaranteed No Missing Codes
n
Serial Interface for Extended Control
n
Fine Adjustment of Input Full-Scale Range and Offset
n
Duty Cycle Corrected Sample Clock
n
Test pattern
Key Specifications
n
Resolution
8 Bits
n
Max Conversion Rate
3 GSPS (min)
n
Bit Error Rate
10
-18
(typ)
n
ENOB
@
748 MHz Input
7.0 Bits (typ)
n
SNR
@
748MHz
44 dB (typ)
n
Full Power Bandwidth
3 GHz (typ)
n
Power Consumption
-- Operating
1.8 W (typ)
-- Power Down Mode
20 mW (typ)
Applications
n
Direct RF Down Conversion
n
Digital Oscilloscopes
n
Satellite Set-top boxes
n
Communications Systems
n
Test Instrumentation
ADVANCE INFORMATION
June 2006
ADC083000
High
Performance,
Low
Power
,
8-Bit,
3
GSPS
A/D
Converter
2006 National Semiconductor Corporation
DS201932
www.national.com
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3
OutV / SCLK
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See Section 1.1.6. When the
extended control mode is enabled, this pin functions as the
SCLK input which clocks in the serial data.See Section 1.2 for
details on the extended control mode. See Section 1.3 for
description of the serial interface.
4
OutEdge / DDR
/ SDATA
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. (See Section 1.1.5.2). When this pin is
floating or connected to 1/2 the supply voltage, DDR clocking
is enabled. When the extended control mode is enabled, this
pin functions as the SDATA input. See Section 1.2 for details
on the extended control mode. See Section 1.3 for description
of the serial interface.
15
DCLK_RST
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See
Section 1.5 for detailed description.
26
PD
Power Down. A logic high on the PD pin puts the entire
device into the Power Down Mode.
30
CAL
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles high
on this pin initiates the self calibration sequence. See Section
2.4.2 for an overview of self-calibration and Section 2.4.2.2 for
a description of on-command calibration.
14
FSR/ECE
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to 650 mV
P-P
. A logic high on
this pin sets the full-scale differential input range to 870
mV
P-P
. See Section 1.1.4. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to V
A
/2. See Section 1.2 for information on the
extended control mode.
127
CalDly / SCS
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 14, this pin functions as Calibration
Delay and sets the number of input clock cycles after power
up before calibration begins (See Section 1.1.1). With pin 14
floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay).
ADC083000
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4
Pin Descriptions and Equivalent Circuits
(Continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
10
11
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 1.1.2 for a
description of acquiring the input and Section 2.3 for an
overview of the clock inputs.
18
19
V
IN
+
V
IN
-
Analog signal inputs to the ADC. The differential full-scale
input range is 650 mV
P-P
when the FSR pin is low, or 870
mV
P-P
when the FSR pin is high.
7
V
CMO
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at V
IN
+ and
V
IN
- when d.c. coupling is used. This pin should be grounded
when a.c. coupling is used at the analog inputs. This pin is
capable of sourcing or sinking 100A. See Section 2.2.
31
V
BG
Bandgap output voltage capable of 100 A source/sink.
126
CalRun
Calibration Running indication. This pin is at a logic high
when calibration is running.
32
R
EXT
External bias resistor connection. Nominal value is 3.3k-Ohms
(
0.1%) to ground. See Section 1.1.1.
34
35
Tdiode_P
Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See Section 2.6.2.
ADC083000
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5
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