ADC08831/ADC08832
8-Bit Serial I/O CMOS A/D Converters with Multiplexer
and Sample/Hold Function
General Description
The ADC08831/ADC08832 are 8-bit successive approxima-
tion Analog to Digital converters with 3-wire serial interfaces
and a configurable input multiplexer for 2 channels. The se-
rial I/O will interface to COPS
TM
family of micro-controllers,
PLD's, microprocessors, DSP's, or shift registers. The serial
I/O is configured to comply with the NSC MICROWIRE
TM
se-
rial data exchange standard.
To
minimize
total
power
consumption,
the
ADC08831/ADC08832 automatically go into low power
mode whenever they are not performing conversions.
A track/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations
of
single-ended,
differential,
or
pseudo-differential modes. The voltage reference input can
be adjusted to allow encoding of small analog voltage spans
to the full 8-bits of resolution.
Applications
n
Digitizing sensors and waveforms
n
Process control monitoring
n
Remote sensing in noisy environments
n
Instrumentation
n
Embedded Systems
Features
n
3-wire serial digital data link requires few I/O pins
n
Analog input track/hold function
n
2-channel input multiplexer option with address logic
n
Analog input voltage range from GND to V
CC
n
No zero or full scale adjustment required
n
TTL/CMOS input/output compatible
n
Superior pin compatible replacement for ADC0831/2
Key Specifications
n
Resolution:
8 bits
n
Conversion time (f
C
= 2 MHz): 4s (max)
n
Power dissipation:
8.5mW (typ)
n
Low power mode: 3.0mW (typ)
n
Single supply:
5V
DC
n
Total unadjusted error:
1LSB
n
No missing codes over temperature
Typical Application
COPS
TM
is a trademark of National Semiconductor Corporation.
MICROWIRE
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
TM
DS100108-44
DS100108-43
September 1999
ADC08831/ADC08832
8-Bit
Serial
I/O
CMOS
A/D
Converters
with
Multiplexer
and
Sample/Hold
Function
1999 National Semiconductor Corporation
DS100108
www.national.com
Connection Diagrams
Ordering Information
Temperature Range
Package
Industrial (-40C
T
J
+85C)
ADC08831IN
N08E
ADC08832IN
ADC08831IWM,
M14B
ADC08832IWM,
ADC08831IM,
M08A
ADC08832IM,
ADC08831IMM,
MUA08A
ADC08832IMM,
ADC08831
Wide Body SO Packages
DS100108-4
ADC08831
N,M,MM Packages
DS100108-2
ADC08832
Wide Body SO Packages
DS100108-3
ADC08832
N,M,MM Packages
DS100108-1
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2
Absolute Maximum Ratings
(Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
6.5V
Voltage at Inputs and Outputs
-0.3V to V
CC
+ 0.3V
Input Current at Any Pin (Note 4)
5 mA
Package Input Current (Note 4)
20 mA
ESD Susceptibility (Note 6)
Human Body Model
2000V
Machine Model
200V
Junction Temperature (Note 5)
150C
Storage Temperature Range
-65 C to 150C
Mounting Temperature
Lead Temp. (soldering, 10 sec)
Infrared (10 sec)
260C
215C
Operating Ratings
(Notes 2, 3)
Temperature Range
-40C
T
J
+85C
Supply Voltage
4.5 V to 6.0 V
Thermal Resistance (
jA
)
SO Package, 8-pin Surface Mount
190C/W
MSOP, 8-pin Surface Mount
235C/W
SO Package, 14-pin Surface Mount
145C/W
N Package, 8-pin
122C/W
Clock Frequency
10kHz
f
CLK
2MHz
Electrical Characteristics
The following specifications apply for V
CC
= V
REF
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
TUE
Total Unadjusted Error
(Note 10)
0.3
1
LSB
(max)
Offset Error
0.2
LSB
DNL
Differential NonLinearity
0.2
LSB
INL
Integral NonLinearity
0.2
LSB
FS
Full Scale Error
0.3
LSB
R
REF
Reference Input Resistance
(Note 11)
3.5
2.8
5.9
k
(min)
k
(max)
V
IN
Analog Input Voltage
(Note 12)
(V
CC
+ 0.05)
(GND - 0.05)
V (max)
V (min)
DC Common-Mode Error
1
/
4
LSB (max)
Power Supply Sensitivity
V
CC
= 5V
10%,
V
CC
= 5V
5%
1
/
4
1
/
4
LSB (max)
LSB (max)
On Channel Leakage Current
(Note 13)
On Channel = 5V,
Off Channel = 0V
0.2
1
A (max)
On Channel = 0V
Off Channel = 5V
-0.2
-1
A (min)
Off Channel Leakage Current
(Note 13)
On Channel = 5V,
Off Channel = 0V
-0.2
-1
A (min)
On Channel = 0V,
Off Channel = 5V
0.2
1
A (max)
DC CHARACTERISTICS
V
IN(1)
Logical "1" Input Voltage
2.0
V (min)
V
IN(0)
Logical "0" Input Voltage
0.8
V (max)
I
IN(1)
Logical "1" Input Current
V
IN
= 5.0V
0.05
+1
A (max)
I
IN(0)
Logical "0" Input Current
V
IN
= 0V
0.05
-1
A (max)
V
OUT(1)
Logical "1" Output Voltage
V
CC
= 4.75V:
I
OUT
= -360 A
2.4
V (min)
I
OUT
= -10 A
4.5
V (min)
V
OUT(0)
Logical "0" Output Voltage
V
CC
= 4.75V
I
OUT
= 1.6 mA
0.4
V (max)
I
OUT
TRI-STATE Output Current
V
OUT
= 0V
V
OUT
= 5V
-3.0
3.0
A (max)
A (max)
I
SOURCE
Output Source Current
V
OUT
= 0V
-6.5
mA (max)
I
SINK
Output Sink Current
V
OUT
= V
CC
8.0
mA (min)
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3
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= V
REF
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
DC CHARACTERISTICS
I
CC
Supply Current
ADC08831
CLK = V
CC
CS = V
CC
0.6
1.0
mA (max)
CS = LOW
1.7
2.4
mA (max)
I
CC
Supply Current
ADC08832
CLK = V
CC
(Note 16)
CS = V
CC
1.3
1.8
mA (max)
CS = LOW
2.4
3.5
mA (max)
Electrical Characteristics
The following specifications apply for V
CC
= V
REF
= +5 V
DC
, and t
r
= t
f
= 20 ns unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
f
CLK
Clock Frequency
2
MHz (max)
Clock Duty Cycle
(Note 14)
40
60
% (min)
% (max)
T
C
Conversion Time (Not Including MUX
Addressing Time)
f
CLK
= 2MHz
8
4
1/f
CLK
(max)
s (max)
t
CA
Acquisition Time
1
/
2
1/f
CLK
(max)
t
SET-UP
CS Falling Edge or Data Input
Valid to CLK Rising Edge
25
ns (min)
t
HOLD
Data Input Valid after CLK
Rising Edge
20
ns (min)
t
pd1
, t
pd0
CLK Falling Edge to Output
Data Valid (Note 15)
C
L
= 100 pF:
Data MSB First
Data LSB First
250
200
ns (max)
ns (max)
t
1H
, t
0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
C
L
= 10 pF, R
L
= 10 k
(see TRI-STATE Test Circuits)
50
ns
C
L
= 100 pF, R
L
= 2 k
180
ns (max)
C
IN
Capacitance of Analog Input (Note 17)
13
pF
C
IN
Capacitance of Logic Inputs
5
pF
C
OUT
Capacitance of Logic Outputs
5
pF
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Dynamic Characteristics
The following specifications apply for V
CC
= 5V, f
CLK
= 2MHz, T
A
= 25C, R
SOURCE
= 50
, f
IN
= 45kHz, V
IN
= 5V
P
, V
REF
= 5V,
non-coherent 2048 samples with windowing.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
f
S
Sampling Rate
ADC08831
ADC08832
f
CLK
/11
f
CLK
/13 (Note 21)
181
153
ksps
ksps
SNR
Signal-to -Noise Ratio (Note 19)
48.5
dB
THD
Total Harmonic Distortion (Note 20)
-59.5
dB
SINAD
Signal-to -Noise and Distortion
48.0
dB
ENOB
Effective Number Of Bits (Note 18)
7.7
Bits
SFDR
Spurious Free Dynamic Range
62.5
dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character-
istics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND = 0 V
DC
, unless otherwise specified.
Note 4: When the input voltage V
IN
at any pin exceeds the power supplies (V
IN
<
(GND) or V
IN
>
V
CC
,) the current at that pin should be limited to 5 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
JA
and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
- T
A
)/
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k
resistor. The machine mode is a 200pF capacitor discharged directly into each pin.
Note 7: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or Linear Data Book section "Surface Mount" for other methods of soldering
surface mount devices.
Note 8: Typicals are at T
J
= 25C and represent the most likely parametric norm.
Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Total Unadjusted Error (TUE) includes offset, full-scale, linearity, multiplexer errors.
Note 11: It is not tested for the ADC08832.
Note 12: For V
IN(-)
V
IN(+)
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will
forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V
CC
supply. During testing at low V
CC
levels (e.g., 4.5V), high
level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code
will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
DC
to 5 V
DC
input voltage
range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two
cases are considered: one, with the selected channel tied high (5 V
DC
) and the remaining off channel tied low (0 V
DC
), total current flow through the off channel is
measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases con-
sidered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 s.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator re-
sponse time.
Note 16: For the ADC08832 V
ref
is internally tied to V
CC
, therefore, for the ADC08832 reference current is included in the supply current.
Note 17: Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor.
Note 18: Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD-1.76)/
6.02.
Note 19: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in it's calculation.
Note 20: The contributions from the first 6 harmonics are used in the calculation of the THD.
Note 21: The maximum sampling rate is slightly less than f
CLK
/11 if CS is reset in less than one clock period.
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