ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep
*
conversion tech-
nique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution "flashes", thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a "speed-up" pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
*
U.S. Patent Number 4918449
Features
n
Built-in sample-and-hold
n
Single +5V supply
n
1, 2, or 4-input multiplexer options
n
No external clock required
n
Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n
Conversion time to 10 bits
600 ns typical,
n
900 ns max over temperature
n
Sampling Rate
800 kHz
n
Low power dissipation
235 mW (max)
n
Total unadjusted error
1.0 LSB (max)
n
No missing codes over temperature
Applications
n
Digital signal processor front ends
n
Instrumentation
n
Disk drives
n
Mobile telecommunications
Simplified Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS011020-1
*
ADC10061 Only
**
ADC10062 and ADC10064 Only
***
ADC10064 Only
June 1999
ADC10061/ADC10062/ADC10064
10-Bit
600
ns
A/D
Converter
with
Input
Multiplexer
and
Sample/Hold
1999 National Semiconductor Corporation
DS011020
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC10061CIWM
M20B Small Outline
ADC10062CIWM
M24B Small Outline
ADC10064CIWM
M28B Small Outline
Connection Diagrams
DS011020-11
Top View
DS011020-12
Top View
DS011020-13
Top View
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2
Pin Descriptions
DV
CC
, AV
CC
These are the digital and analog positive sup-
ply voltage inputs. They should always be con-
nected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 F ceramic capacitor in
parallel with a 10 F tantalum capacitor to
ground.
INT
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
S/H
This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and ini-
tiates a new conversion.
RD
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
CS
This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
S0, S1
On the multiple-input devices (ADC10062 and
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Dia-
grams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
V
REF-
,
V
REF+
These are the reference voltage inputs. They
may be placed at any voltage between GND
and V
CC
, but V
REF+
must be greater than
V
REF-
. An input voltage equal to V
REF-
pro-
duces an output code of 0, and an input volt-
age equal to (V
REF+
- 1 LSB) produces an out-
put code of 1023.
V
IN
, V
IN0
,
V
IN1
, V
IN2
,
V
IN3
These
are
the
analog
input
pins.
The
ADC10061 has one input (V
IN
), the ADC10062
has two inputs (V
IN0
and V
IN1
), and the
ADC10064 has four inputs (V
IN0
, V
IN1
, V
IN2
and V
IN3
). The impedance of the source
should be less than 500
for best accuracy
and conversion speed. For accurate conver-
sions, no input pin (even one that is not se-
lected) should be driven more than 50 mV
above V
CC
or 50 mV below ground.
GND, AGND,
DGND
These are the power supply ground pins. The
ADC10061 has a single ground pin (GND),
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
pins
should be
connected to a
stable,
noise-free system ground. For the devices
with two ground pins, both pins should be re-
turned to the same potential.
DB0DB9
These are the TRI-STATE
output pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the con-
version time can be reduced. See the Typical
Performance Curves and the table of Electri-
cal Characteristics.
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3
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
= AV
CC
= DV
CC
)
-0.3V to +6V
Voltage at Any Input or Output
-0.3V to V
+
+ 0.3V
Input Current at Any Pin (Note 3)
5 mA
Package Input Current (Note 3)
20 mA
Power Dissipation (Note 4)
875 mW
ESD Susceptability (Note 5)
2000V
Soldering Information (Note 6)
Vapor Phase (60 Sec)
Infrared (15 Sec)
215C
220C
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
Operating Ratings
(Notes 1, 2)
Temperature Range
T
MIN
T
A
T
MAX
ADC10061CIWM,
ADC10062CIWM,
ADC10064CIWM
-40C
T
A
+85C
Supply Voltage Range
4.5V to 5.5V
Converter Characteristics
The following specifications apply for V
+
= +5V, V
REF(+)
= +5V, V
REF(-)
= GND, and Speed Adjust pin unconnected unless
otherwise specified. Boldface limits apply for T
A
= T
J
= T
Min
to T
Max
; all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Resolution
10
Bits
Integral Linearity Error
R
SA
= 18 k
0.5
1.0/
1.5
LSB (max)
Offset Error
1
LSB (max)
Full-Scale Error
1
LSB (max)
Total Unadjusted Error
All Suffixes, R
SA
= 18 k
0.5
1.5/
2.0
LSB (max)
Missing Codes
0
(max)
Power Supply Sensitivity
V
+
= 5V
5%, V
REF
= 4.5V
V
+
= 5V
10%, V
REF
= 4.5V
1/16
3
/
8
LSB
LSB (max)
THD
Total Harmonic Distortion
f
IN
= 10 kHz, 4.85 V
P-P
f
IN
= 160 kHz, 4.85 V
P-P
0.06
0.08
%
%
SNR
Signal-to-Noise Ratio
f
IN
= 10 kHz, 4.85 V
P-P
f
IN
= 160 kHz, 4.85 V
P-P
61
60
dB
dB
Effective Number of Bits
f
IN
= 10 kHz, 4.85 V
P-P
f
IN
= 160 kHz, 4.85 V
P-P
9.6
9.4
Bits
Bits
R
REF
Reference Resistance
650
400
(min)
R
REF
Reference Resistance
650
900
(max)
V
REF(+)
V
REF(+)
Input Voltage
V
+
+ 0.05
V (max)
V
REF(-)
V
REF(-)
Input Voltage
GND - 0.05
V (min)
V
REF(+)
V
REF(+)
Input Voltage
V
REF(-)
V (min)
V
REF(-)
V
REF(-)
Input Voltage
V
REF(+)
V (max)
V
IN
Input Voltage
V
+
+ 0.05
V (max)
V
IN
Input Voltage
GND - 0.05
V (min)
OFF Channel Input Leakage Current
ON Channel Input Leakage Current
CS = V
+
, V
IN
= V
+
CS = V
+
, V
IN
= V
+
0.01
1
3
-3
A (max)
A (max)
DC Electrical Characteristics
The following specifications apply for V
+
= +5V, V
REF(+)
= 5V V
REF(-)
= GND, and Speed Adjust pin unconnected unless other-
wise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
V
IN(1)
Logical "1" Input Voltage
V
+
= 5.5V
2.0
V (min)
V
IN(0)
Logical "0" Input Voltage
V
+
= 4.5V
0.8
V (max)
I
IN(1)
Logical "1" Input Current
V
IN(1)
= 5V
0.005
3.0
A (max)
I
IN(0)
Logical "0" Input Current
V
IN(0)
0V
-0.005
-3.0
A (max)
V
OUT(1)
Logical "1" Output Voltage
V
+
= 4.5V, I
OUT
= -360 A
V
+
= 4.5V, I
OUT
= -10 A
2.4
4.25
V (min)
V (min)
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4
DC Electrical Characteristics
(Continued)
The following specifications apply for V
+
= +5V, V
REF(+)
= 5V V
REF(-)
= GND, and Speed Adjust pin unconnected unless other-
wise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
V
OUT(0)
Logical "0" Output Voltage
V
+
= 4.5V, I
OUT
= 1.6 mA
0.4
V (max)
I
OUT
TRI-STATE
Output Current
V
OUT
= 5V
V
OUT
= 0V
0.1
-0.1
50
-50
A (max)
A (max)
DI
CC
DV
CC
Supply Current
CS = S/H = RD = 0, R
SA
=
CS = S/H = RD = 0, R
SA
= 18 k
1.0
1.0
2
mA (max)
mA (max)
AI
CC
AV
CC
Supply Current
CS = S/H = RD = 0, R
SA
=
CS = S/H = RD = 0, R
SA
= 18 k
30
30
45
mA (max)
mA (max)
AC Electrical Characteristics
The following specifications apply for V
+
= +5V, t
r
= t
f
= 20 ns, V
REF(+)
= 5V, V
REF(-)
= GND, and Speed Adjust pin uncon-
nected unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
t
CONV
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
R
SA
=
R
SA
= 18k
600
375
750/900
ns(max)
ns
t
CRD
Mode 2 Conversion Time
R
SA
=
Mode 2, R
SA
= 18k
850
530
1400
ns(max)
ns
t
ACC1
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 1; C
L
= 100 pF
30
60
ns (max)
t
ACC2
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 2; C
L
= 100 pF
900
t
CRD
+ 50
ns (max)
t
SH
Minimum Sample Time
(
Figure 1); (Note 8)
250
ns (max)
t
1H
, t
0H
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
R
L
= 1k, C
L
= 10 pF
30
60
ns (max)
t
INTH
Delay from Rising Edge of RD to
Rising Edge of INT
C
L
= 100 pF
25
50
ns (max)
t
P
Delay from End of Conversion to
Next Conversion
50
ns (max)
t
MS
Multiplexer Control Setup Time
10
75
ns (max)
t
MH
Multiplexer Hold Time
10
40
ns (max)
C
VIN
Analog Input Capacitance
35
pF (max)
C
OUT
Logic Output Capacitance
5
pF (max)
C
IN
Logic Input Capacitance
5
pF (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
GND or V
IN
>
V
+
) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
JA
and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
- T
A
)/
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
JMAX
for a board-mounted device can be found from the
tables below:
Device
JA
(C/W)
ADC10061CIWM
54
ADC10062CIWM
48
ADC10064CIWM
44
Note 5: Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25C and represent must likely parametric norm.
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5
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