ADC108S102
8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter
General Description
The ADC108S102 is a low-power, eight-channel CMOS 10-
bit analog-to-digital converter specified for conversion
throughput rates of 500 kSPS to 1 MSPS. The converter is
based on a successive-approximation register architecture
with an internal track-and-hold circuit. It can be configured to
accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible
with several standards, such as SPI
TM
, QSPI
TM
, MICROW-
IRE
TM
, and many common DSP serial interfaces.
The ADC108S102 may be operated with independent ana-
log and digital supplies. The analog supply (V
A
) can range
from +2.7V to +5.25V, and the digital supply (V
D
) can range
from +2.7V to V
A
. Normal power consumption using a +3V or
+5V supply is 2.1 mW and 9.4 mW, respectively. The power-
down feature reduces the power consumption to 0.09 W
using a +3V supply and 0.30 W using a +5V supply.
The ADC108S102 is packaged in a 16-lead TSSOP pack-
age. Operation over the extended industrial temperature
range of -40C to +105C is guaranteed.
Features
n
Eight input channels
n
Variable power management
n
Independent analog and digital supplies
n
SPI/QSPI/MICROWIRE/DSP compatible
n
Packaged in 16-lead TSSOP
Key Specifications
n
Conversion Rate
500 kSPS to 1 MSPS
n
DNL (V
A
= V
D
= 5.0 V)
0.5 LSB (max)
n
INL (V
A
= V
D
= 5.0 V)
0.5 LSB (max)
n
Power Consumption
-- 3V Supply
2.1 mW (typ)
-- 5V Supply
9.4 mW (typ)
Applications
n
Automotive Navigation
n
Portable Systems
n
Medical Instruments
n
Mobile Communications
n
Instrumentation and Control Systems
Connection Diagram
20164305
Ordering Information
Order Code
Temperature Range
Description
ADC108S102CIMT
-40C to +105C
16-Lead TSSOP Package
ADC108S102CIMTX
-40C to +105C
16-Lead TSSOP Package, Tape & Reel
ADC108S102EVAL
Evaluation Board
TRI-STATE
is a trademark of National Semiconductor Corporation.
MICROWIRE
TM
is a trademark of National Semiconductor Corporation.
QSPI
TM
and SPI
TM
are trademarks of Motorola, Inc.
September 2005
ADC108S102
8-Channel,
500
kSPS
to
1
MSPS,
10-Bit
A/D
Converter
2005 National Semiconductor Corporation
DS201643
www.national.com
Block Diagram
20164307
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
4 - 11
IN0 to IN7
Analog inputs. These signals can range from 0V to V
REF
.
DIGITAL I/O
16
SCLK
Digital clock input. The guaranteed performance range of
frequencies for this input is 8 MHz to 16 MHz. This clock
directly controls the conversion and readout processes.
15
DOUT
Digital data output. The output samples are clocked out of this
pin on the falling edges of the SCLK pin.
14
DIN
Digital data input. The ADC108S102's Control Register is
loaded through this pin on rising edges of the SCLK pin.
1
CS
Chip select. On the falling edge of CS, a conversion process
begins. Conversions continue as long as CS is held low.
POWER SUPPLY
2
V
A
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet
+2.7V to +5.25V source and bypassed to GND with 1 F and
0.1 F monolithic ceramic capacitors located within 1 cm of
the power pin.
13
V
D
Positive digital supply pin. This pin should be connected to a
+2.7V to V
A
supply, and bypassed to GND with a 0.1 F
monolithic ceramic capacitor located within 1 cm of the power
pin.
3
AGND
The ground return for the analog supply and signals.
12
DGND
The ground return for the digital supply and signals.
ADC108S102
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage V
A
-0.3V to 6.5V
Digital Supply Voltage V
D
-0.3V to V
A
+ 0.3V,
max 6.5V
Voltage on Any Pin to GND
-0.3V to V
A
+0.3V
Input Current at Any Pin (Note 3)
10 mA
Package Input Current(Note 3)
20 mA
Power Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
2500V
250V
Soldering Temperature, Infrared,
10 seconds (Note 6)
260C
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature
-40C
T
A
+105C
V
A
Supply Voltage
+2.7V to +5.25V
V
D
Supply Voltage
+2.7V to V
A
Digital Input Voltage
0V to V
A
Analog Input Voltage
0V to V
A
Clock Frequency
8 MHz to 16 MHz
Package Thermal Resistance
Package
JA
16-lead TSSOP on
4-layer, 2 oz. PCB
96C / W
Soldering process must comply with National Semiconduc-
tor's Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)
ADC108S102 Converter Electrical Characteristics
(Note 8)
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
=
500 kSPS to 1 MSPS, and C
L
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits
T
A
= 25C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
10
Bits
INL
Integral Non-Linearity (End Point
Method)
0.2
0.5
LSB (max)
DNL
Differential Non-Linearity
0.2
0.5
LSB (max)
V
OFF
Offset Error
+0.3
0.7
LSB (max)
OEM
Offset Error Match
0.07
0.4
LSB (max)
FSE
Full Scale Error
+0.2
0.4
LSB (max)
FSEM
Full Scale Error Match
0.07
0.4
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth (-3dB)
8
MHz
SINAD
Signal-to-Noise Plus Distortion Ratio
f
IN
= 40.2 kHz, -0.02 dBFS
61.8
61.3
dB (min)
SNR
Signal-to-Noise Ratio
f
IN
= 40.2 kHz, -0.02 dBFS
61.8
61.4
dB (min)
THD
Total Harmonic Distortion
f
IN
= 40.2 kHz, -0.02 dBFS
-87.0
-73.8
dB (max)
SFDR
Spurious-Free Dynamic Range
f
IN
= 40.2 kHz, -0.02 dBFS
83.1
76.0
dB (min)
ENOB
Effective Number of Bits
f
IN
= 40.2 kHz
9.98
9.89
Bits (min)
ISO
Channel-to-Channel Isolation
f
IN
= 20 kHz
79.7
dB
IMD
Intermodulation Distortion, Second
Order Terms
f
a
= 19.5 kHz, f
b
= 20.5 kHz
-83.9
dB
Intermodulation Distortion, Third
Order Terms
f
a
= 19.5 kHz, f
b
= 20.5 kHz
-82.4
dB
ANALOG INPUT CHARACTERISTICS
V
IN
Input Range
0 to V
A
V
I
DCL
DC Leakage Current
1
A (max)
C
INA
Input Capacitance
Track Mode
33
pF
Hold Mode
3
pF
ADC108S102
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3
ADC108S102 Converter Electrical Characteristics
(Note 8) (Continued)
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
=
500 kSPS to 1 MSPS, and C
L
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits
T
A
= 25C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
DIGITAL INPUT CHARACTERISTICS
V
IH
Input High Voltage
V
A
= V
D
= +2.7V to +3.6V
2.1
V (min)
V
A
= V
D
= +4.75V to +5.25V
2.4
V (min)
V
IL
Input Low Voltage
V
A
= V
D
= +2.7V to +5.25V
0.8
V (max)
I
IN
Input Current
V
IN
= 0V or V
D
0.01
1
A (max)
C
IND
Digital Input Capacitance
2
4
pF (max)
DIGITAL OUTPUT CHARACTERISTICS
V
OH
Output High Voltage
I
SOURCE
= 200 A
V
D
- 0.5
V (min)
V
OL
Output Low Voltage
I
SINK
= 200 A to 1.0 mA,
0.4
V (max)
I
OZH
, I
OZL
Hi-Impedance Output Leakage
Current
1
A (max)
C
OUT
Hi-Impedance Output Capacitance
(Note 8)
2
4
pF (max)
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
V
A
, V
D
Analog and Digital Supply Voltages
V
A
V
D
2.7
V (min)
5.25
V (max)
I
A
+ I
D
Total Supply Current
Normal Mode ( CS low)
V
A
= V
D
= +2.7V to +3.6V,
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
0.70
1.4
mA (max)
V
A
= V
D
= +4.75V to +5.25V,
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
1.88
2.7
mA (max)
Total Supply Current
Shutdown Mode (CS high)
V
A
= V
D
= +2.7V to +3.6V,
f
SCLK
= 0 kSPS
30
nA
V
A
= V
D
= +4.75V to +5.25V,
f
SCLK
= 0 kSPS
60
nA
P
C
Power Consumption
Normal Mode ( CS low)
V
A
= V
D
= +3.0V
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
2.1
4.2
mW (max)
V
A
= V
D
= +5.0V
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
9.4
13.6
mW (max)
Power Consumption
Shutdown Mode (CS high)
V
A
= V
D
= +3.0V
f
SCLK
= 0 kSPS
0.09
W
V
A
= V
D
= +5.0V
f
SCLK
= 0 kSPS
0.30
W
AC ELECTRICAL CHARACTERISTICS
f
SCLK
MIN
Minimum Clock Frequency
0.8
8
MHz (min)
f
SCLK
Maximum Clock Frequency
16
MHz (max)
f
S
Sample Rate
Continuous Mode
50
500
kSPS (min)
1
MSPS (max)
t
CONVERT
Conversion (Hold) Time
13
SCLK cycles
DC
SCLK Duty Cycle
30
40
% (min)
70
60
% (max)
t
ACQ
Acquisition (Track) Time
3
SCLK cycles
Throughput Time
Acquisition Time + Conversion Time
16
SCLK cycles
t
AD
Aperture Delay
4
ns
ADC108S102
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4
ADC108S102 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
=
500 kSPS to 1 MSPS, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
t
CSH
CS Hold Time after SCLK Rising
Edge
(Note 9)
0
10
ns (min)
t
CSS
CS Setup Time prior to SCLK Rising
Edge
(Note 9)
5
10
ns (min)
t
EN
CS Falling Edge to DOUT enabled
5
30
ns (max)
t
DACC
DOUT Access Time after SCLK
Falling Edge
17
27
ns (max)
t
DHLD
DOUT Hold Time after SCLK Falling
Edge
4
ns (typ)
t
DS
DIN Setup Time prior to SCLK
Rising Edge
3
10
ns (min)
t
DH
DIN Hold Time after SCLK Rising
Edge
3
10
ns (min)
t
CH
SCLK High Time
0.4 x
t
SCLK
ns (min)
t
CL
SCLK Low Time
0.4 x
t
SCLK
ns (min)
t
DIS
CS Rising Edge to DOUT
High-Impedance
DOUT falling
2.4
20
ns (max)
DOUT rising
0.9
20
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
IN
<
AGND or V
IN
>
V
A
or V
D
), the current at that pin should be limited to 10 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (T
J
max) for this device is 150C. The maximum allowable power dissipation is dictated by T
J
max, the
junction-to-ambient thermal resistance (
JA
), and the ambient temperature (T
A
), and can be calculated using the formula P
D
MAX = (T
J
max - T
A
)/
JA
. In the 16-pin
TSSOP,
JA
is 96C/W, so P
D
MAX = 1,200 mW at 25C and 625 mW at the maximum operating ambient temperature of 105C. Note that the power consumption
of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC108S102
is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k
resistor. Machine model is 220 pF discharged through ZERO ohms
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Clock may be in any state (high or low) when CS goes high. Setup and hold restrictions apply only to CS going low.
ADC108S102
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