ADC12040
12-Bit, 40 MSPS, 340 mW A/D Converter with Internal
Sample-and-Hold
General Description
The ADC12040 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 40 Megasamples per second (MSPS), mini-
mum. This converter uses a differential, pipeline architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption while
providing excellent dynamic performance. Operating on a
single 5V power supply, this device consumes just 340 mW
at 40 MSPS, including the reference current. The Power
Down feature reduces power consumption to 40 mW.
The differential inputs provide a full scale input swing equal
to V
REF
with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of -40C to
+85C.
Features
n
Single supply operation
n
Internal sample-and-hold
n
Outputs 2.5V to 5V compatible
n
TTL/CMOS compatible input/outputs
n
Low power consumption
n
Power down mode
n
On-chip reference buffer
Key Specifications
n
Resolution
12 Bits
n
Conversion Rate
40 MSPS (min)
n
DNL
0.4 LSB (typ)
n
INL
0.7 LSB (typ)
n
SNR (f
IN
= 10MHz)
69 dB (typ)
n
ENOB (f
IN
= 10MHz)
11.2 bits (typ)
n
Data Latency
6 Clock Cycles
n
Supply Voltage
+5V
5%
n
Power Consumption, 40 MHz
340 mW (typ)
Applications
n
Ultrasound and Imaging
n
Instrumentation
n
Cellular Base Stations/Communications Receivers
n
Sonar/Radar
n
xDSL
n
Wireless Local Loops/Cable Modems
n
HDTV/DTV
n
DSP Front Ends
Connection Diagram
20014801
June 2003
ADC12040
12-Bit,
40
MSPS,
340
mW
A/D
Converter
with
Internal
Sample-and-Hold
2003 National Semiconductor Corporation
DS200148
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC12040CIVY
32 Pin LQFP
ADC12040CIVYX
32 Pin LQFP Tape and Reel
ADC12040EVAL
Evaluation Board
Block Diagram
20014802
ADC12040
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2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2
V
IN+
Non-Inverting analog signal Input. With a 2.0V reference
voltage, the differential input signal level is 2.0 V
P-P
centered
on V
CM
.
3
V
IN-
Inverting analog signal Input. With a 2.0V reference voltage
the input signal level is 2.0 V
P-P
centered on V
CM
. This pin
may be connected to V
CM
for single-ended operation, but a
differential input signal is required for best performance.
1
V
REF
Reference input. This pin should be bypassed to AGND with
a 0.1 F monolithic capacitor. V
REF
is 2.0V nominal and
should be between 1.0V to 2.2V.
31
V
RP
These pins are high impedance reference bypass pins only.
Connect a 0.1 F capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
32
V
RM
30
V
RN
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is
100 kHz to 50 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
11
OE
OE is the output enable pin that, when low, enables the
TRI-STATE
TM
data output pins. When this pin is high, the
outputs are in a high impedance state.
8
PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
ADC12040
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3
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
1419,
2227
D0D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word. Output levels are TTL/CMOS compatible.
ANALOG POWER
5, 6, 29
V
A
Positive analog supply pins. These pins should be connected
to a quiet +5V voltage source and bypassed to AGND with
0.1 F monolithic capacitors located within 1 cm of these
power pins, and with a 10 F capacitor.
4, 7, 28
AGND
The ground return for the analog supply.
DIGITAL POWER
13
V
D
Positive digital supply pin. This pin should be connected to
the same quiet +5V source as is V
A
and bypassed to DGND
with a 0.1 F monolithic capacitor in parallel with a 10 F
capacitor, both located within 1 cm of the power pin.
9, 12
DGND
The ground return for the digital supply.
21
V
DR
Positive digital supply pin for the ADC12040's output drivers.
This pin should be connected to a voltage source of +2.5V to
+5V and bypassed to DR GND with a 0.1 F monolithic
capacitor. If the supply for this pin is different from the supply
used for V
A
and V
D
, it should also be bypassed with a 10 F
tantalum capacitor. V
DR
should never exceed the voltage on
V
D
. All bypass capacitors should be located within 1 cm of the
supply pin.
20
DR GND
The ground return for the digital supply for the ADC12040's
output drivers. This pin should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12040's DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
ADC12040
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A
, V
D
, V
DR
6.5V
|V
A
V
D
|
100 mV
Voltage on Any Input or Output Pin
-0.3V to (V
A
or V
D
+0.3V)
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Package Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature,
Infrared, 10 sec. (Note 6)
235C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature
-40C
T
A
+85C
Supply Voltage (V
A
, V
D
)
+4.75V to +5.25V
Output Driver Supply (V
DR
)
+2.35V to V
D
V
REF
Input
1.0V to 2.2V
CLK, PD, OE
-0.05V to (V
D
+ 0.05V)
V
IN
Input
-0V to (V
A
- 0.5V)
|AGNDDGND|
100mV
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A
= V
D
= +5V, V
DR
=
+3.0V, PD = 0V, V
REF
= +2.0V, f
CLK
= 40 MHz, t
r
= t
f
= 3 ns, C
L
= 20 pF/pin. Boldface limits apply for T
A
= T
J
= T
MIN
to
T
MAX
: all other limits T
A
= T
J
= 25C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits (min)
INL
Integral Non Linearity (Note 11)
0.7
1.8
LSB (max)
DNL
Differential Non Linearity
0.4
1.0
LSB (max)
GE
Gain Error
0.1
2.1
%FS (max)
Offset Error (V
IN
+ = V
IN
-)
-0.1
0.9
%FS (max)
Under Range Output Code
0
0
Over Range Output Code
4095
4095
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
0 dBFS Input, Output at -3 dB
100
MHz
SNR
Signal-to-Noise Ratio
f
IN
1 MHz, V
IN
-0.5 dBFS
70
dB
f
IN
= 10 MHz, V
IN
= -0.5 dBFS
69.5
66.5
dB (min)
SINAD
Signal-to-Noise and Distortion
f
IN
= 1 MHz, V
IN
= -0.5 dBFS
69.5
dB
f
IN
= 10 MHz, V
IN
= -0.5 dBFS
69
66
dB (min)
ENOB
Effective Number of Bits
f
IN
= 1 MHz, V
IN
= -0,5 dBFS
11.2
Bits
f
IN
= 10 MHz, V
IN
= -0,5 dBFS
11.2
10.7
Bits (min)
THD
Total Harmonic Distortion
f
IN
= 1 MHz, V
IN
= -0,5 dBFS
-82
dB
f
IN
= 10 MHz, V
IN
= -0,5 dBFS
-80
-67
dB (max)
SFDR
Spurious Free Dynamic Range
f
IN
= 1 MHz, V
IN
= -0,5 dBFS
86
dB
f
IN
= 10 MHz, V
IN
= -0.5 dBFS
84
-68
dB (min)
IMD
Intermodulation Distortion
f
IN
= 9.5 MHz and 10.5 MHz,
each = -8 dBFS
-75
dBFS
ADC12040
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