ADC12DL065
Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter
General Description
The ADC12DL065 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 65 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 250
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC12DL065 achieves 11.0 effective bits
at nyquist and consumes just 360 mW at 65 MSPS, including
the reference current. The Power Down feature reduces
power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC's are available on a single multiplexed 12-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two's comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL065 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of -40C to +85C. An evaluation board is
available to ease the evaluation process.
Features
n
Single +3.3V supply operation
n
Internal sample-and-hold
n
Internal reference
n
Outputs 2.4V to 3.6V compatible
n
Power down mode
n
Duty Cycle Stabilizer
n
Multiplexed Output Mode
Key Specifications
n
Resolution
12 Bits
n
DNL
0.4 LSB (typ)
n
SNR (f
IN
= 10 MHz)
69 dB (typ)
n
SFDR (f
IN
= 10 MHz)
86 dB (typ)
n
Data Latency
7 Clock Cycles
n
Power Consumption
n
-- Operating
360 mW (typ)
n
-- Power Down Mode
36 mW (typ)
Applications
n
Ultrasound and Imaging
n
Instrumentation
n
Communications Receivers
n
Sonar/Radar
n
xDSL
n
Cable Modems
n
DSP Front Ends
Connection Diagram
20100101
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
May 2005
ADC12DL065
Dual
12-Bit,
65
MSPS,
3.3V
,
360mW
A/D
Converter
2005 National Semiconductor Corporation
DS201001
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC12DL065CIVS
64 Pin TQFP
ADC12DL065EVAL
Evaluation Board
Block Diagram
20100102
ADC12DL065
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2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
15
2
V
IN
A+
V
IN
B+
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
P-P
with each
input pin voltage centered on a common mode voltage, V
CM
.
The negative input pins may be connected to V
CM
for
single-ended operation, but a differential input signal is
required for best performance.
16
1
V
IN
A-
V
IN
B-
7
V
REF
This pin is the reference select pin and the external reference
input.
If (V
A
- 0.3V)
<
V
REF
<
V
A
, the internal 1.0V reference is
selected.
If AGND
<
V
REF
<
(AGND + 0.3V), the internal 0.5V reference
is selected.
If a voltage in the range of 0.8V to 1.2V is applied to this pin,
that voltage is used as the reference. V
REF
should be
bypassed to AGND with a 0.1 F capacitor when an external
reference is used.
21
DF/DCS
This is a four-state pin.
DF/DCS = V
A
, output data format is offset binary with duty
cycle stabilization applied to the input clock
DF/DCS = AGND, output data format is 2's complement, with
duty cycle stabilization applied to the input clock.
DF/DCS = V
RM
A or V
RM
B , output data is 2's complement
without duty cycle stabilization applied to the input clock
DF/DCS = "float", output data is offset binary without duty cycle
stabilization applied to the input clock.
13
5
V
RP
A
V
RP
B
These pins are high impedance reference bypass pins. All
these pins should each be bypassed to ground with a 0.1 F
capacitor. A 10 F capacitor should be placed between the
V
RP
A and V
RN
A pins and between the V
RP
B and V
RN
B pins.
V
RM
A and V
RM
B may be loaded to 1mA for use as a
temperature stable 1.5V reference. The remaining pins should
not be loaded.
14
4
V
RM
A
V
RM
B
12
6
V
RN
A
V
RN
B
DIGITAL I/O
60
CLK
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 65 MHz. The input is sampled on the rising edge.
22
41
OEA
OEB
OEA and OEB are the output enable pins that, when low, holds
their respective data output pins in the active state. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
ADC12DL065
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3
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
59
PD
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
11
MULTIPLEX
When low, "A" & "B" data is present on it's respective data
output lines (Parallel Mode).
When high, both "A" and "B" channel data is present on the
"DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin
is used to synchronize the data.
2429
3439
DA0DA11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output word.
Output levels are TTL/CMOS compatible. Optimum loading is
<
10pF.
4347
5257
DB1DB11
42
DB0/ABb
When MULTIPLEX is low, this is DB0.
When MULTIPLEX is high this is the ABb signal, which is used
to synchronize the multiplexed data. ABb changes
synchronously with the Multiplexed "A" and "B" channels. ABb
is "high" when "A" channel data is valid and is "low" when "B"
channel data is valid.
ANALOG POWER
9, 18, 19,
62, 63
V
A
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and bypassed to AGND with 0.1 F
capacitors located within 1 cm of these power pins, and with a
10 F capacitor.
3, 8, 10, 17,
20, 61, 64
AGND
The ground return for the analog supply.
DIGITAL POWER
33, 48
V
D
Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is V
A
and be bypassed to DGND
with a 0.1 F capacitor located within 1 cm of the power pin
and with a 10 F capacitor.
32, 49
DGND
The ground return for the digital supply.
30, 51
V
DR
Positive driver supply pin for the ADC12DL065's output drivers.
This pin should be connected to a voltage source of +2.4V to
V
D
and be bypassed to DR GND with a 0.1 F capacitor. If the
supply for this pin is different from the supply used for V
A
and
V
D
, it should also be bypassed with a 10 F capacitor. V
DR
should never exceed the voltage on V
D
. All 0.1 F bypass
capacitors should be located within 1 cm of the supply pin.
23, 31, 40,
50, 58
DR GND
The ground return for the digital supply for the ADC12DL065's
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12DL065's DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
ADC12DL065
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A
, V
D
, V
DR
4.2V
|V
A
V
D
|
100 mV
Voltage on Any Input or Output Pin
-0.3V to (V
A
or V
D
+0.3V)
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Package Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature,
Infrared, 10 sec. (Note 6)
235C
Storage Temperature
-65C to +150C
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to
www.national.com/packaging.(Note 6)
Operating Ratings
(Notes 1, 2)
Operating Temperature
-40C
T
A
+85C
Supply Voltage (V
A
, V
D
)
+3.0V to +3.6V
Output Driver Supply (V
DR
)
+2.4V to V
D
CLK, PD, OEA, OEB
-0.05V to (V
D
+ 0.05V)
Analog Input Pins
0V to 2.6V
V
CM
0.5V to 2.0V
|AGNDDGND|
100mV
Clock Duty Cycle (DCS On)
20% to 80%
Clock Duty Cycle (DCS Off)
40% to 60%
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A
= V
D
= +3.3V, V
DR
=
+2.5V, PD = 0V, External V
REF
= +1.0V, f
CLK
= 65 MHz, f
IN
= 10 MHz, t
r
= t
f
= 2 ns, C
L
= 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits (min)
INL
Integral Non Linearity (Note 11)
0.75
1.7
LSB (max)
DNL
Differential Non Linearity
0.4
1.0
LSB (max)
PGE
Positive Gain Error
0.2
2.9
%FS (max)
NGE
Negative Gain Error
0.2
3.2
%FS (max)
TC GE
Gain Error Tempco
-40C
T
A
+85C
10
ppm/C
V
OFF
Offset Error (V
IN
+ = V
IN
-)
0.18
0.85
%FS (max)
%FS (min)
TC
V
OFF
Offset Error Tempco
-40C
T
A
+85C
3.6
ppm/C
Under Range Output Code
0
0
Over Range Output Code
4095
4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
Common Mode Input Voltage
1.5
0.5
V (min)
2.0
V (max)
V
RM
A,
V
RM
B
Reference Output Voltage
Output load = 1 mA
1.5
V
C
IN
V
IN
Input Capacitance (each pin to
GND)
V
IN
= 2.5 Vdc
+ 0.7 V
rms
(CLK LOW)
8
pF
(CLK HIGH)
7
pF
V
REF
External Reference Voltage (Note
13)
1.00
0.8
V (min)
1.2
V (max)
Reference Input Resistance
1
M
(min)
DYNAMIC CONVERTER CHARACTERISTICS
ADC12DL065
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