TL H 10409
ADC9708
6-Channel
8-Bit
m
P
Compatible
AD
Converter
October 1991
ADC9708
6-Channel 8-Bit mP Compatible A D Converter
General Description
The ADC9708 is a single slope 8-bit 6-channel ADC sub-
system that provides all of the necessary analog functions
for a microprocessor-based data control system The device
uses an external microprocessor system to provide the nec-
essary addressing timing and counting functions and in-
cludes a 1-of-8 decoder 8-channel analog multiplexer sam-
ple and hold ramp integrator precision ramp reference and
a comparator on a single monolithic chip
Features
Y
MPU compatible
Y
Excellent linearity over full temperature
range
g
0 2% maximum
Y
Typical 300 ms conversion time per channel
Y
Wide dynamic range includes ground
Y
Auto-zero and full-scale correction capability
Y
Ratiometric conversion
no precision reference
required
Y
Single-supply operation
Y
TTL compatible
Y
Does not require access to data bus or address bus
Connection Diagram
All Packages
TL H 10409 2
(Top View)
Ordering Information
Commercial (0 C
s
T
A
s
70 C)
Package
ADC9708CCN
N16E
ADC9708CCJ
J16A
Military (
b
55 C
s
T
A
s
125 C)
Package
ADC9708CMJ
J16A
Block Diagram
TL H 10409 1
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
18V
Comparator Output (Ramp Stop)
b
0 3V to
a
18V
Analog Input Range
b
0 3V to
a
30V
Digital Input Range
b
0 3V to
a
30V
Output Sink Current
10 mA
Storage Temperature Range
b
65 C to
a
150 C
Continuous Total Dissipation (Note 8)
Ceramic DIP Package
900 mW
Molded DIP Package
1000 mW
ESD Susceptibility (Note 9)
TBD
Pin Temperature
Ceramic DIP (Soldering 60 Sec )
300 C
Molded DIP (Soldering 10 Sec )
260 C
Operating Ratings
(Notes 1 2)
Operating Temperature Range
ADC9708CCN ADC9708CCJ
0 C to
a
70 C
ADC9708CMJ
b
55 C to
a
125 C
Supply Voltage (V
CC
)
4 75V to 15V
Reference Voltage
(V
REF
) (Note 3)
2 8V to 5 25V
Ramp Capacitor (C
H
)
300 pF
Reference Current (I
R
)
12 mA to 50 mA
Analog Input Range
0V to V
REF
Ramp Stop Output Current
1 6 mA
Electrical Characteristics
Over recommended operating conditions V
CC
e
5 0V
b
55 C
s
T
A
s
a
125 C for ADC9708CMJ and 0 C
s
T
A
s
a
70 C for
ADC9708CCJ or ADC9708CCN unless otherwise specified
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 10)
(Note 11)
(Limit)
E
A
Conversion Accuracy
Over Entire Temperature
g
0 2
g
0 3
% (max)
Range (Note 4)
E
R
Linearity
Applies to Any One
g
0 08
g
0 2
% (max)
Channel (Note 5)
V
OSM
Multiplexer Input Offset Voltage
Channel ON T
A
e
25 C
2 0
4 0
mV (max)
Channel ON
2 0
7 0
mV (max)
t
C
Conversion Time per Channel
Analog Input
e
0V to V
REF
296
350
m
s (max)
C
H
e
300 pF I
REF
e
50 mA
t
A
Acquisition Time
C
H
e
1000 pF
20
40
m
s (max)
I
A
Acquisition Current
ADC9708CCN CCJ
150
m
A (min)
ADC9708CMJ
115
m
A (min)
t
O
Ramp Start Delay Time
100
ns
t
M
Multiplexer Address Time
1 0
m
s
V
IH
Digital Input HIGH Voltage
A0 A1 A2 Ramp Start
2 0
V (min)
V
IL
Digital Input LOW Voltage
A0 A1 A2 Ramp Start
0 8
V
I
B
Analog Input Current
Channel ON or OFF
b
1 0
b
3 0
m
A (min)
I
IL
Input LOW Current
A0 A1 A2 Ramp Start
e
0 4V
b
5
b
15
m
A (min)
I
IH
Input HIGH Current
A0 A1 A2 Ramp Start
e
5 5V
1 0
m
A (max)
I
OS
Input Offset Current
1 0
3 0
m
A (max)
I
OH
Comparator Logic ``1''
V
OH
e
15V
10
m
A (max)
Output Leakage Current
V
OL
Comparator Logic ``0'' Output
I
OL
e
1 6 mA
0 4
V (max)
Voltage
PSRR
Power Supply Rejection Ratio
(Note 6)
40
dB (min)
Cross Talk between
(Note 7)
60
dB (min)
Any Two Channels
2
Electrical Characteristics
Over recommended operating conditions V
CC
e
5 0V
b
55 C
s
T
A
s
a
125 C for ADC9708CMJ and 0 C
s
T
A
s
a
70 C for
ADC9708CCJ or ADC9708CCN unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 10)
(Note 11)
(Limit)
I
CC
Power Supply Current
V
CC
e
5V to 15V I0
e
0
7 5
15
mA (max)
C
IN
Input Capacitance
3 0
pF
C
OUT
Comparator Output Capacitance
5 0
pF
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
intended to be functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the
Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device
is not operated under the listed test conditions
Note 2
All voltages are measured with respect to GND unless otherwise specified
Note 3
V
REF
should not exceed V
CC
b
2V
Note 4
Conversion accuracy is defined as the deviations from a straight line drawn between the points defined by channel address 000 (0 scale) and channel
address 111 (full scale) for all channels
Note 5
Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel
Note 6
Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel
Note 7
Cross Talk between channels
e
20 log
D
V
CH
D
V
I
Note 8
Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
(maximum junction
temperature) i
JA
(package junction to ambient thermal resistance) and T
A
(ambient temperature) The maximum allowable power dissipation at any temperature
is P
Dmax
e
(T
Jmax
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For this device T
Jmax
e
150 C and the typical thermal
resistance (i
JA
) for board mounting follow
ADC9708CCN
62 C W
ADC9708CCJ ADC9708CMJ
58 C W
Note 9
Human body model 100 pF discharged through a 1 5 kX resistor
Timing Diagram
TL H 10409 7
FIGURE 1 Equivalent Timing Waveform for
Test Circuits and Applications
Note 10
Typicals are at
a
25 C and represent most likely parametric norm
Note 11
Tested limits are guaranteed to National's AOQL (Average Outgo-
ing Quality Level)
Test Circuits
Input Timing
TL H 10409 8
t
A
l
400 ms
V
REF
e
3 3 kX
2 kX
a
3 3 kX
J
5V
e
3 1
I
R
e
5
b
3 1
100 kX
e
19 mA
t
R
l
max
e
full scale ramp time
e
0 01
c
10
b
6
19
c
10
b
6
c
3 1
e
1 6 ms
Note
For evaluation purposes the ramp start timing generation can be im-
plemented with an LM555 timer (astable operation) or MPU evaluation kit
and a time interval meter for ramp time measurement The TIM meter will
measure the time between to 0 to 1 transition of the ramp start and the 1 to
0 transition of the ramp stop The ramp stop is open collector and must
have an external pull-up resistor to V
CC
FIGURE 2 Slow Speed Evaluation Circuit
for Ratiometric Operation
3
Test Circuits
(Continued)
TL H 10409 9
FIGURE 3 Linearity Acquisition Time
Conversion Time Test Circuit
TL H 10409 10
FIGURE 4 Static Measurements
Functional Description
This Analog to Digital Converter is a single-slope 8-bit
6-channel A D converter that provides all of the necessary
analog functions for a microprocessor-based data control
system The device uses the processor system to provide
the necessary addressing timing and counting functions
and includes a 1-of-8 decoder 8-channel analog multiplex-
er sample and hold precision current reference ramp inte-
grator and comparator on a single monolithic chip
Applications that require auto-zero or auto-calibration (See
Figures 5 8 ) can use selection of address 000 and 111 for
input address lines A0 A2 in conjunction with the arithme-
tic capability of a microprocessor to provide ground and
scaling factors Address 0 0 0 internally connects the input
of the ramp generator to ground and may be used for zero
offset correction in subsequent conversions Address 1 1
1 internally connects the input of the ramp generator to the
voltage reference V
REF
and may be used for scale factor
correction in subsequent conversions For the following re-
fer to the Functional Block Diagram
Six separate external analog voltage inputs may come into
terminals I1 I6 and the specific analog input to be convert-
ed is selected via address terminals A0 A2 The analog
input voltage level is transferred to the external ramp capac-
itor connected to pin 4 when the input to the ramp start
terminal (pin 3) is at a logic 0 (See
Figure 1 ) The time to
charge the capacitor is the acquisition time which is a func-
tion of the output impedance of an amplifier internal to the
A D converter and the value of the capacitor After charging
the external capacitor the ramp start terminal is switched to
a logic 1 which introduces a high impedance between the
analog input voltage and the external capacitor
The capacitor begins to discharge at a controlled rate The
controlled rate of discharge (ramp) is established by the ex-
ternal reference voltage the external reference resistor the
value of the external capacitor and the internal leakage of
the A D converter Connected to the capacitor terminal is a
comparator internal to the A D converter with its output go-
ing to the ramp stop terminal (pin 7) The comparator output
is a logic one when the capacitor is charged and switches to
a logic 0 when the capacitor is in a discharged state The
ramp time is from the time when ramp start goes HIGH (log-
ic ``1'') to when ramp stop goes LOW (logic ``0'') The micro-
processor must be programmed to determine this conver-
sion time The ideal (no undesirable internal source imped-
ances leakage paths errors on levels where comparator
switches or delay time) conversion time is calculated as fol-
lows
Ramp Time
e
V1
C
H
I
R
Where
V1
e
Analog Input Voltage Being Measured
C
H
e
External Ramp Capacitor
I
R
e
V
CC
b
V
REF
R
REF
Where
V
CC
e
Power Supply Voltage
V
REF
e
Reference Voltage
R
REF
e
Reference Resistor
In actual use the errors due to a nonideal A D converter can
be minimized by using a microprocessor to make the calcu-
lations (See
Figures 5 through 8 )
Channel Selection
Input Address Line
Selected
A2
A1
A0
Analog Input
0
0
0
Ground
0
0
1
I1
0
1
0
I2
0
1
1
I3
1
0
0
I4
1
0
1
I5
1
1
0
I6
1
1
1
V
REF
4
Functional Description
(Continued)
Auto-Zero and Full-Scale Features
No Zero Offset
TL H 10409 3
No Full-Scale Error
Count (n)
e
V
IN
V
REF
c
256
FIGURE 5 Ideal Transfer Function
N
F S
i
256
TL H 10409 4
N
Z
i
0
(N) has both full-scale and zero errors
FIGURE 6 Transfer Function with
Zero and Full-Scale Error
N
e
N
b
N
Z
TL H 10409 5
N has Full-Scale Error
FIGURE 7 Transfer Functions with
Zero-Correction Added
TL H 10409 6
N
e
(N
b
N
Z
)
c
256
(N
F S
b
N
Z
)
FIGURE 8 Transfer Function with both Zero and
Full-Scale Correction Added
Typical Applications
Application Suggestions and Formulas
1 The capacitor node impedance is approximately 30 mX
and should have no parallel resistance for proper opera-
tion
2 t
R
when V
IN
e
0V will be finite (i e the comparator will
always toggle for V
IN
t
0V)
3 The ramp stop output is open collector and an external
pull-up resistor is required
4 All digital inputs and outputs are TTL compatible
5 For proper operation timing commences on the 0 to 1
transition of ramp start and terminates on the 1 to 0 tran-
sition of ramp stop
6 t
A
t
C
H
I
A
b
I
R
c
V
REF
(See
Figure 1 )
7 t
R
(ramp time)
e
C
H
I
R
c
V
IN
t
R
l
max
e
C
H
I
R
c
V
REF
(See
Figure 1 )
8 I
R
e
V
CC
b
V
REF
R
REF
9 2V
s
V
REF
s
(V
CC
b
2V)
10 Address lines A0 A1 A2 must be stable throughout the
sampling interval t
A
11 Pin 6 (R
REF
) should be bypassed to ground via a 0 02
m
F capacitor
Microprocessor Considerations
Several alternatives exist from a hardware software stand-
point in microprocessor based systems using the ADC9708
1 The ramp time measurement may be implemented in
software using a register increment followed by a branch
back depending on the status of the ramp stop
2 Alternately the ramp stop may be tied into the interrupt
structure in systems containing a programmable binary
timer This scheme has the following advantages
a The CPU is not committed during the ramp time inter-
val
b It requires only 5 bits of an I O port for control signals
5
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