TL F 5962
CD4031BMCD4031BC
64-Stage
Static
Shift
Register
February 1988
CD4031BM CD4031BC
64-Stage Static Shift Register
General Description
The CD4031BM CD4031BC is an integrated complemen-
tary MOS (CMOS) 64-stage fully static shift register Two
data inputs DATA IN and RECIRCULATE IN and a MODE
CONTROL input are provided Data at the DATA input
(when MODE CONTROL is low) or data at the RECIRCU-
LATE input (when MODE CONTROL is high) which meets
the setup and hold time requirements is entered into the
first stage of the register and is shifted one stage at each
positive transition of the CLOCK
Data output is available in both true and complement forms
from the 64th stage Both the DATA OUT (Q) AND DATA
OUT (Q) outputs are fully buffered
The CLOCK input of the CD4031BM CD4031BC is fully
buffered and present only a standard input load capaci-
tance However a DELAYED CLOCK OUTPUT (CL
D
) has
been provided to allow reduced clock drive fan-out and tran-
sition time requirements when cascading packages
Features
Y
Wide supply voltage range
3 0V to 15V
Y
High noise immunity
0 45 V
DD
(typ )
Y
Low power TTL
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y
Fully static operation
DC to 8 MHz
V
DD
e
10V (typ )
Y
Fully buffered clock input
5 pF (typ )
input capacitance
Y
Single phase clocking requirements
Y
Delayed clock output for reduced clock drive require-
ments
Y
Fully buffered outputs
Y
High current sinking capability
1 6 mA
Y
Q output
V
DD
e
5V and 25 C
Logic and Connection Diagrams
TL F 5962 1
Dual-In-Line Package
TL F 5962 2
Top View
Order Number CD4031B
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
DD
)
b
0 5V to
a
18V
Input Voltage (V
IN
)
b
0 5V to V
DD
a
0 5V
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temp (T
L
) (Soldering 10 sec )
260 C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
DD
)
3V to 15V
Input Voltage (V
IN
)
0V to V
DD
Operating Temperature Range (T
A
)
CD4031BM
b
55 C to
a
125 C
CD4031BC
b
40 C to
a
85 C
DC Electrical Characteristics
(Note 2) CD4031BM
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
5
0 01
5
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
10
0 01
10
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
20
0 02
20
600
m
A
V
OL
Low Level Output
V
DD
e
5V
0 05
0
0 05
0 05
V
Voltage
V
DD
e
10V
V
IH
e
V
DD
V
IL
e
0V
l
I
O
l
k
1 mA
0 05
0
0 05
0 05
V
V
DD
e
15V
(
0 05
0
0 05
0 05
V
V
OH
High Level Output
V
DD
e
5V
4 95
4 95
5
4 95
V
Voltage
V
DD
e
10V
V
IH
e
V
DD
V
IL
e
0V
l
I
O
l
k
1 mA 9 95
9 95
10
9 95
V
V
DD
e
15V
(
14 95
14 95
15
14 95
V
V
IL
Low Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
2 25
1 5
1 5
V
Voltage
V
DD
e
10V V
O
e
1 0V or 9 0V
l
I
O
l
k
1 mA
3 0
4 5
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
(
4 0
6 75
4 0
4 0
V
V
IH
High Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
2 75
3 5
V
Voltage
V
DD
e
10V V
O
e
1 0V or 9 0V
l
I
O
l
k
1 mA
7 0
7 0
5 5
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
(
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
V
IH
e
V
DD
2 3
1 9
3 8
1 3
mA
Current Q Output
V
DD
e
10V V
O
e
0 5V
V
IL
e
0V
5 1
4 2
8 4
2 8
mA
(Note 3)
V
DD
e
15V V
O
e
1 5V
(
10 5
8 8
17
6 1
mA
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
V
IH
e
V
DD
0 64
0 51
0 88
0 36
mA
Current Q and CL
D
V
DD
e
10V V
O
e
0 5V
V
IL
e
0V
1 6
1 3
2 25
0 9
mA
Outputs (Note 3)
V
D
e
15V V
O
e
1 5V
(
4 2
3 4
8 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
V
IH
e
V
DD
b
0 64
b
0 51
b
0 88
b
0 36
mA
Current All Outputs V
DD
e
10V V
O
e
9 5V
V
IL
e
0V
b
1 6
b
1 3
b
2 25
b
0 9
mA
(Note 3)
V
DD
e
15V V
O
e
13 5V
(
b
4 2
b
3 4
b
8 8
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 1
b
10
b
5
b
0 1
b
1 0 mA
V
DD
e
15V V
IN
e
15V
0 1
10
b
5
0 1
1 0
m
A
Truth Tables
Mode Control (Data Selection)
Mode
Data
Recirculate
Data Into
Control
In
In
First Stage
0
0
X
0
0
1
X
1
1
X
0
0
1
X
1
1
Each Stage
D
n
CL
Q
n
0
L
0
1
L
1
X
K
NC
X
e
irrelevant
NC
e
no change
L
e
Low to High level transition
K
e
High to Low level transition
2
DC Electrical Characteristics
(Note 2) CD4031BC
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
20
0 01
20
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
40
0 01
40
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
80
0 02
80
600
m
A
V
OL
Low Level Output
V
DD
e
5V
0 05
0
0 05
0 05
V
Voltage
V
DD
e
10V
V
IH
e
V
DD
V
IL
e
0V
l
I
O
l
k
1 mA
0 05
0
0 05
0 05
V
V
DD
e
15V
(
0 05
0
0 05
0 05
V
V
OH
High Level Output
V
DD
e
5V
4 95
4 95
5
4 95
V
Voltage
V
DD
e
10V
V
IH
e
V
DD
V
IL
e
0V
l
I
O
l
k
1 mA 9 95
9 95
10
9 95
V
V
DD
e
15V
(
14 95
14 95
15
14 95
V
V
IL
Low Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
2 25
1 5
1 5
V
Voltage
V
DD
e
10V V
O
e
1 0V or 9 0V
l
I
O
l
k
1 mA
3 0
4 5
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
(
4 0
6 75
4 0
4 0
V
V
IH
High Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
2 75
3 5
V
Voltage
V
DD
e
10V V
O
e
1 0V or 9 0V
l
I
O
l
k
1 mA
7 0
7 0
5 5
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
(
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
V
IH
e
V
DD
1 8
1 6
3 8
1 3
mA
Current Q Output
V
DD
e
10V V
O
e
0 5V
V
IL
e
0V
4 0
3 5
8 4
2 8
mA
(Note 3)
V
DD
e
15V V
O
e
1 5V
(
8 7
7 5
17
6 1
mA
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
V
IH
e
V
DD
0 52
0 44
0 88
0 36
mA
Current Q and CL
D
V
DD
e
10V V
O
e
0 5V
V
IL
e
0V
1 3
1 1
2 25
0 9
mA
Outputs
V
DD
e
15V V
O
e
1 5V
(
3 6
3 0
8 8
2 4
mA
(Note 3)
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
V
IH
e
V
DD
b
0 52
b
0 44
b
0 88
b
0 36
mA
Current All Outputs V
DD
e
10V V
O
e
9 5V
V
IL
e
0V
b
1 3
b
1 1
b
2 25
b
0 9
mA
(Note 3)
V
DD
e
15V V
O
e
13 5V
(
b
3 0
b
3 0
b
8 8
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 3
b
10
b
5
b
0 3
b
1 0 mA
V
DD
e
15V V
IN
e
15V
0 3
10
b
5
0 3
1 0
m
A
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of `Recommended Operating Conditions'' and ``Electrical Characteristics'' provide conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Switching Time Waveforms
TL F 5962 3
3
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF R
L
e
200k Input t
r
e
t
f
e
20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
t
PLH
Propagation Delay Time Clock to Q and Q
V
CC
e
5V
300
600
ns
V
CC
e
10V
125
250
ns
V
CC
e
15V
100
200
ns
t
PHL
t
PLH
Propagation Delay Time Clock to CL
D
V
CC
e
5V
125
250
ns
V
CC
e
10V
60
125
ns
V
CC
e
15V
50
100
ns
t
THL
t
TLH
Output Transition Time All Outputs
V
CC
e
5V
100
200
ns
V
CC
e
10V
50
100
ns
V
CC
e
15V
40
80
ns
t
SU0
Minimum Data Setup Time DATA IN or
V
CC
e
5V
100
200
ns
t
SU1
RECIRCULATE IN to Clock
V
CC
e
10V
50
100
ns
V
CC
e
15V
40
80
ns
t
H0
Minimum Data Hold Time Clock to DATA IN
V
CC
e
5V
100
200
ns
t
H1
or RECIRCULATE IN
V
CC
e
10V
50
100
ns
V
CC
e
15V
40
80
ns
t
WL
t
WH
Minimum Clock Pulse Width
V
CC
e
5V
150
30
ns
V
CC
e
10V
60
125
ns
V
CC
e
15V
50
100
ns
f
CL
Maximum Clock Frequency
V
CC
e
5V
1 6
3 2
MHz
V
CC
e
10V
4 0
8 0
MHz
V
CC
e
15V
5 0
10
MHz
t
RCL
t
FCL
Maximum Clock Input Rise and Fall Times
V
CC
e
5V
15
m
s
(Note 4)
V
CC
e
10V
10
m
s
V
CC
e
15V
5
m
s
C
IN
Input Capacitance
Any Input
5
7 5
pF
AC Parameters are guaranteed by DC correlated testing
Note 4
When clocking cascaded packages in parallel one should insure that t
r CL
s
2 (t
PD
b
t
H
) where t
PD
e
the propagation delay of the driving stage
and t
H
e
the hold time of the driven stage
Block Diagram
cascading packages using DELAYED CLOCK (CL
D
) output
TL F 5962 4
4
Physical Dimensions
inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4031BMJ or CD4031BCJ
NS Package Number J16A
5
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