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Электронный компонент: CD4541

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TL F 6001
CD4541BMCD4541BC
Programmable
Timer
February 1988
CD4541BM CD4541BC Programmable Timer
General Description
The CD4541B Programmable Timer is designed with a
16-stage binary counter an integrated oscillator for use with
an external capacitor and two resistors output control logic
and a special power-on reset circuit The special features of
the power-on reset circuit are first no additional static pow-
er consumption and second the part functions across the
full voltage range (3V 15V) whether power-on reset is en-
abled or disabled
Timing and the counter are initialized by turning on power if
the power-on reset is enabled When the power is already
on an external reset pulse will also initialize the timing and
counter After either reset is accomplished the oscillator
frequency is determined by the external RC network The
16-stage counter divides the oscillator frequency by any of 4
digitally controlled division ratios
Features
Y
Available division ratios 2
8
2
10
2
13
or 2
16
Y
Increments on positive edge clock transitions
Y
Built-in low power RC oscillator (
g
2% accuracy over
temperature range and
g
10% supply and
g
3% over
processing
k
10 kHz)
Y
Oscillator frequency range
DC to 100 kHz
Y
Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
Y
Automatic reset initializes all counters when power
turns on
Y
External master reset totally independent of automatic
reset operation
Y
Operates at 2
n
frequency divider or single transition
timer
Y
Q Q select provides output logic level flexibility
Y
Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
Y
Clock conditioning circuit permits operation with very
slow clock rise and fall times
Y
Wide supply voltage range
3 0V to 15V
Y
High noise immunity
0 45 V
DD
(typ )
Y
5V 10V 15V parameter ratings
Y
Symmetrical output characteristics
Y
Maximum input leakage 1 mA at 15V over full tempera-
ture range
Y
High output drive (pin 8) min one TTL load
Logic Diagram
V
DD
e
Pin 14
V
SS
e
Pin 7
TL F 6001 1
Connection Diagram
Dual-In-Line Package
Order Number CD4541B
N C
Not connected
TL F 6001 2
Top View
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
DD
)
b
0 5V to
a
18V
Input Voltage (V
IN
)
b
0 5V to V
DD
a
0 5V
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
) (soldering 10 sec )
260 C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
DD
)
3V to 15V
Input Voltage (V
IN
)
0 to V
DD
Operating Temperature Range
CD4541BM
b
55 C to
a
125 C
CD4541BC
b
40 C to
a
85 C
DC Electrical Characteristics
(Note 2)
CD4541BM
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V V
IN
e
V
DD
or V
SS
5
0 005
5
150
m
A
V
DD
e
10V V
IN
e
V
DD
or V
SS
10
0 010
10
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
20
0 015
20
600
m
A
V
OL
Low Level Output Voltage V
DD
e
5V
0 05
0
0 05
0 05
V
V
DD
e
10V
l
I
O
l
k
1 mA
0 05
0
0 05
0 05
V
V
DD
e
15V
0 05
0
0 05
0 05
V
V
OH
High Level Output Voltage V
DD
e
5V
4 95
4 95
5
4 95
V
V
DD
e
10V
l
I
O
l
k
1 mA
9 95
9 95
10
9 95
V
V
DD
e
15V
14 95
14 95
15
14 95
V
V
IL
Low Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
2
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
4
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
6
4 0
4 0
V
V
IH
High Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
6
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
9
11 0
V
I
OL
Low Level Output Current
V
DD
e
5V V
O
e
0 4V
2 85
2 27
3 6
1 6
mA
(Note 3)
V
DD
e
10V V
O
e
0 5V
4 96
4 0
9 0
2 8
mA
V
DD
e
15V V
O
e
1 5V
19 3
15 6
34 0
10 9
mA
I
OH
High Level Output Current V
DD
e
5V V
O
e
2 5V
7 96
6 42
13 0
4 49
mA
(Note 3)
V
DD
e
10V V
O
e
9 5V
4 19
3 38
8 0
2 37
mA
V
DD
e
15V V
O
e
3 5V
16 3
13 2
30 0
9 24
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 10
b
10
b
5
b
0 10
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 10
10
b
5
0 10
1 0
m
A
DC Electrical Characteristics
(Note 2)
CD4541BC
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V V
IN
e
V
DD
or V
SS
20
0 005
20
150
m
A
V
DD
e
10V V
IN
e
V
DD
or V
SS
40
0 010
40
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
80
0 015
80
600
m
A
V
OL
Low Level Output Voltage
V
DD
e
5V
0 05
0
0 05
0 05
V
V
DD
e
10V
l
I
O
l
k
1mA
0 05
0
0 05
0 05
V
V
DD
e
15V
0 05
0
0 05
0 05
V
V
OH
High Level Output Voltage
V
DD
e
5V
4 95
4 95
5
4 95
V
V
DD
e
10V
l
I
O
l
k
1 mA
9 95
9 95
10
9 95
V
V
DD
e
15V
14 95
14 95
15
14 95
V
V
IL
Low Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
2
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
4
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
6
4 0
4 0
V
2
DC Electrical Characteristics
(Note 2)
CD4541BC (Continued)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
V
IH
High Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
6
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
9
11 0
V
I
OL
Low Level Output Current
V
DD
e
5V V
O
e
0 4V
2 32
1 96
3 6
1 6
mA
(Note 3)
V
DD
e
10V V
O
e
0 5V
3 18
2 66
9 0
2 18
mA
V
DD
e
15V V
O
e
1 5V
12 4
10 4
34 0
8 50
mA
I
OH
High Level Output Current
V
DD
e
5V V
O
e
2 5V
5 1
4 27
130
3 5
mA
(Note 3)
V
DD
e
10V V
O
e
9 5V
2 69
2 25
8 0
1 85
mA
V
DD
e
15V V
O
e
13 5V
10 5
8 8
30 0
7 22
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 3
b
10
b
5
b
0 3
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 3
10
b
5
0 3
1 0
m
A
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF (refer to test circuits)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
TLH
Output Rise Time
V
DD
e
5V
50
200
ns
V
DD
e
10V
30
100
ns
V
DD
e
15V
25
80
ns
t
THL
Output Fall Time
V
DD
e
5V
50
200
ns
V
DD
e
10V
30
100
ns
V
DD
e
15V
25
80
ns
t
PLH
t
PHL
Turn-Off Turn-On Propagation Delay
V
DD
e
5V
1 8
4 0
m
s
Clock to Q (2
8
Output)
V
DD
e
10V
0 6
1 5
m
s
V
DD
e
15V
0 4
1 0
m
s
t
PHL
t
PLH
Turn-On Turn-Off Propagation Delay
V
DD
e
5V
3 2
8 0
m
s
Clock to Q (2
16
Output)
V
DD
e
10V
1 5
3 0
m
s
V
DD
e
15V
1 0
2 0
m
s
t
WH(CL)
Clock Pulse Width
V
DD
e
5V
400
200
ns
V
DD
e
10V
200
100
ns
V
DD
e
15V
150
70
ns
f
CL
Clock Pulse Frequency
V
DD
e
5V
2 5
1 0
MHz
V
DD
e
10V
6 0
3 0
MHz
V
DD
e
15V
8 5
4 0
MHz
t
WH(R)
MR Pulse Width
V
DD
e
5V
400
170
ns
V
DD
e
10V
200
75
ns
V
DD
e
15V
150
50
ns
C
I
Average Input Capacitance
Any Input
5 0
7 5
pF
C
PD
Power Dissipation Capacitance (Note 4)
100
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Note 4
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C family characteristics application note
AN-90
3
Truth Table
Pin
State
0
1
5
Auto Reset Operating
Auto Reset Disabled
6
Timer Operational
Master Reset On
9
Output Initially Low
Output Initially High
after Reset
after Reset
10
Single Cycle Mode
Recycle Mode
Division Ratio Table
Number of
Count
A
B
Counter Stages
2
n
n
0
0
13
8192
0
1
10
1024
1
0
8
256
1
1
16
65536
Operating Characteristics
With Auto Reset pin set to a ``0'' the counter circuit is initial-
ized by turning on power Or with power already on the
counter circuit is reset when the Master Reset pin is set to a
``1'' Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state
The RC oscillator frequency is determined by the external
RC network i e
f
e
1
2 3 R
tc
C
tc
if (1 kHz
s
f
s
100 kHz)
and R
S
2 R
tc
where R
S
t
10 kX
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2
8
2
10
2
13
and
2
16
) The 2
n
counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter
When A is ``1'' 2
16
is selected for both states of B
However when B is ``0'' normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i e effectively outputting 2
8
)
The Q Q select output control pin provides for a choice of
output level When the counter is in a reset condition and
Q Q select pin is set to a ``0'' the Q output is a ``0'' Corre-
spondingly when Q Q select pin is set to a ``1'' the Q output
is a ``1''
When the mode control pin is set to a ``1'' the selected
count is continually transmitted to the output But with
mode pin ``0'' and after a reset condition the RS flip-flop
resets (see Logic Diagram) counting commences and after
2
nb1
counts the RS flip-flop sets which causes the output
to change state Hence after another 2
nb1
counts the out-
put will not change Thus a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation
Power Dissipation Test
Circuit and Waveforms
(R
tc
and C
tc
outputs are left open)
TL F 6001 3
Switching Time Test
Circuit and Waveforms
TL F 6001 4
TL F 6001 5
TL F 6001 6
4
Operating Characteristics
(Continued)
Oscillator Circuit Using RC Configuration
TL F 6001 7
Typical RC Oscillator
Characteristics
TL F 6001 8
Solid Line
e
R
TC
e
56 kX R
S
e
1 kX and C
e
1000 pF
f
e
10 2 kHz
V
DD
e
10V and T
A
e
25 C
Dashed Line
e
R
TC
e
56 kX R
S
e
120 kX and C
e
1000 pF
f
e
7 75 kHz
V
DD
e
10V and T
A
e
25 C
RC Oscillator Frequency as a
Function of R
TC
and C
TL F 6001 9
Line A f as a function of C and (R
TC
e
56 kX R
S
e
120k)
Line B f as a function of R
TC
and (C
e
100 pF R
S
e
2 R
TC
)
5