TL F 6631
DM54L74
Dual
Positive-Edge-Triggered
D
Flip-Flops
with
Preset
Clear
and
Complementary
Outputs
June 1989
DM54L74 Dual Positive-Edge-Triggered D Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs The informa-
tion on the D input is accepted by the flip-flops on the posi-
tive going edge of the clock pulse The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock The data on the D input
may be changed while the clock is low or high without af-
fecting the outputs as long as the data setup and hold times
are not violated A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs
Connection Diagram
Dual-In-Line Package
TL F 6631 1
Order Number DM54L74J or DM54L74W
See NS Package Number J14A or W14B
Function Table
Inputs
Outputs
PR
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
u
H
H
L
H
H
u
L
L
H
H
H
L
X
Q
O
Q
O
H
e
High Logic Level
X
e
Either Low or High Logic Level
L
e
Low Logic Level
u
e
Positive-going transition
Q
O
e
The output logic level of Q before the indicated input conditions were
established
e
This configuration is nonstable that is it will not persist when either the
preset and or clear inputs returned to their inactive (high) level
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
8V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54L
b
55 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54L74
Units
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Current
b
0 2
mA
I
OL
Low Level Output Current
2
mA
f
CLK
Clock Frequency (Note 2)
0
6
MHz
t
W
Pulse Width (Note 2)
Clock High
75
Clock Low
75
ns
Preset Low
75
Clear Low
75
t
SU
Input Setup Time (Notes 1
2)
50
u
ns
t
H
Input Hold Time (Notes 1
2)
15
u
ns
T
A
Free Air Operating Temperature
b
55
125
C
Note 1
The symbol (
u
) indicates the rising edge of the clock pulse is used for reference
Note 2
T
A
e
25 C and V
CC
e
5V
2
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
2 4
3 3
V
Voltage
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
0 15
0 3
V
Voltage
V
IL
e
Max V
IH
e
Min
I
I
Input Current
Max
V
CC
e
Max
D
100
Input Voltage
V
I
e
5 5V
Clear
300
m
A
Preset
200
Clock
200
I
IH
High Level Input
V
CC
e
Max
D
10
Current
V
I
e
2 4V
Clear
30
m
A
Preset
20
Clock
20
I
IL
Low Level Input
V
CC
e
Max
D
b
0 18
Current
V
I
e
0 3V
Clear
b
0 36
mA
Preset
b
0 18
Clock
b
0 36
I
OS
Short Circuit
V
CC
e
Max
b
3
b
15
mA
Output Current
I
CC
Supply Current
V
CC
e
Max (Note 2)
1 6
3
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
With all outputs open I
CC
is measured with the Q and Q outputs high in turn At the time of measurement the clock input is grounded
Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
R
L
e
4 kX C
L
e
50 pF
Units
To (Output)
Min
Max
f
MAX
Maximum Clock Frequency
6
MHz
t
PLH
Propagation Delay Time
Preset
60
ns
Low to High Level Output
to Q
t
PHL
Propagation Delay Time
Preset
120
ns
High to Low Level Output
to Q
t
PLH
Propagation Delay Time
Clear
60
ns
Low to High Level Output
to Q
t
PHL
Propagation Delay Time
Clear
120
ns
High to Low Level Output
to Q
t
PLH
Propagation Delay Time
Clock to
10
90
ns
Low to High Level Output
Q or Q
t
PHL
Propagation Delay Time
Clock to
10
120
ns
High to Low Level Output
Q or Q
3
DM54L74
Dual
Positive-Edge-Triggered
D
Flip-Flops
with
Preset
Clear
and
Complementary
Outputs
Physical Dimensions
inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54L74J
NS Package Number J14A
14-Lead Ceramic Flat Package (W)
Order Number DM54L74W
NS Package Number W14B
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effectiveness
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