TL F 6476
DM54S195DM74S195
4-Bit
Parallel
Access
Shift
Registers
June 1989
DM54S195 DM74S195 4-Bit Parallel Access
Shift Registers
General Description
These 4-bit registers feature parallel inputs parallel outputs
J-K serial inputs shift load control input and a direct over-
riding clear All inputs are buffered to lower the input drive
requirements The registers have two modes of operation
Parallel (broadside) load
Shift (in the direction Q
A
toward Q
D
)
Parallel loading is accomplished by applying the four bits of
data and taking the shift load control input low The data is
loaded into the associated flip-flop and appears at the out-
puts after the positive transition of the clock input During
loading serial data flow is inhibited
Shifting is accomplished synchronously when the shift load
control input is high Serial data for this mode is entered at
the J-K inputs These inputs permit the first stage to perform
as a J-K D or T-type flip-flop as shown in the truth table
The high-performance S195 with a 105 MHz typical shift
frequency is particularly attractive for very high-speed data
processing systems In most cases existing systems can be
upgraded merely by using this Schottky-clamped shift regis-
ter
Features
Y
Synchronous parallel load
Y
Positive-edge-triggered clocking
Y
Parallel inputs and outputs from each flip-flop
Y
Direct overriding clear
Y
J and K inputs to first stage
Y
Complementary outputs from last stage
Y
For use in high-performance
accumulators processors
serial-to-parallel parallel-to-serial converters
Y
Typical clock frequency 105 MHz
Y
Typical power dissipation 350 mW
Connection Diagram
Dual-In-Line Package
TL F 6476 1
Order Number DM54S195J or DM74S195N
See NS Package Number J16A or N16E
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54S
b
55 C to
a
125 C
DM74S
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54S195
DM74S195
Units
Min
Nom
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 8
0 8
V
I
OH
High Level Output Current
b
1
b
1
mA
I
OL
Low Level Output Current
20
20
mA
f
CLK
Clock Frequency (Note 1)
0
105
70
0
105
70
MHz
f
CLK
Clock Frequency (Note 2)
0
90
60
0
90
60
MHz
t
W
Pulse Width
Clock
7
7
ns
(Note 3)
Clear
12
12
t
SU
Setup Time
Shift Load
11
11
ns
(Note 3)
Data
5
5
t
H
Data Hold Time (Note 3)
3
3
ns
t
REL
Shift Load Release Time (Note 3)
6
6
ns
Clear Release Time (Note 3)
9
9
T
A
Free Air Operating Temperature
b
55
125
0
70
C
Note 1
C
L
e
15 pF R
L
e
280X T
A
e
25 C and V
CC
e
5V
Note 2
C
L
e
50 pF R
L
e
280X T
A
e
25 C and V
CC
e
5V
Note 3
T
A
e
25 C and V
CC
e
5V
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 4)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
18 mA
b
1 2
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
DM54
2 5
3 4
V
Voltage
V
IL
e
Max V
IH
e
Min
DM74
2 7
3 4
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
0 5
V
Voltage
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 7V
50
m
A
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 5V
b
2
mA
I
OS
Short Circuit
V
CC
e
Max
DM54
b
40
b
100
mA
Output Current
(Note 5)
DM74
b
40
b
100
I
CC
Supply Current
V
CC
e
Max (Note 6)
70
109
mA
Note 4
All typicals are at V
CC
e
5V T
A
e
25 C
Note 5
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 6
With all inputs open SHIFT LOAD grounded and 4 5V applied to the J K and data inputs I
CC
is measured by applying a momentary ground then 4 5V to
the CLEAR and then applying a momentary ground then 4 5V to the CLOCK
2
Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
R
L
e
280X
Symbol
Parameter
From (Input)
C
L
e
15 pF
C
L
e
50 pF
Units
To (Output)
Min
Max
Min
Max
f
MAX
Maximum Clock
70
60
MHz
Frequency
t
PLH
Propagation Delay Time
Clock to
12
15
ns
Low to High Level Output
Any Q
t
PHL
Propagation Delay Time
Clock to
16 5
20
ns
High to Low Level Output
Any Q
t
PHL
Propagation Delay Time
Clear to
18 5
23
ns
High to Low Level Output
Any Q
Function Table
Inputs
Outputs
Clear
Shift
Clock
Serial
Parallel
Q
A
Q
B
Q
C
Q
D
Q
D
Load
J
K
A
B
C
D
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
L
u
X
X
a
b
c
d
a
b
c
d
d
H
H
L
X
X
X
X
X
X
Q
A0
Q
B0
Q
C0
Q
D0
Q
D0
H
H
u
L
H
X
X
X
X
Q
A0
Q
A0
Q
Bn
Q
Cn
Q
Cn
H
H
u
L
L
X
X
X
X
L
Q
An
Q
Bn
Q
Cn
Q
Cn
H
H
u
H
H
X
X
X
X
H
Q
An
Q
Bn
Q
Cn
Q
Cn
H
H
u
H
L
X
X
X
X
Q
An
Q
An
Q
Bn
Q
Cn
Q
Cn
H
e
High Level (steady state) L
e
Low Level (steady state) X
e
Don't Care (any input including transitions)
u
e
Transition from low to high level
a b c d
e
The level of steady state input at A B C or D respectively
Q
A0
Q
B0
Q
C0
Q
D0
e
The level of Q
A
Q
B
Q
C
or Q
D
respectively before the indicated steady state input conditions were established
Q
An
Q
Bn
Q
Cn
e
The level of Q
A
Q
B
Q
C
respectively before the most recent transition of the clock
Logic Diagram
TL F 6476 2
3
Timing Diagram
Typical Clear Shift and Load Sequences
TL F 6476 3
4
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54S195J
NS Package Number J16A
5
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