TL F 10385

DP83241

CDD

Device

(FDDI

Clock

Distribution

Device)

February 1991

DP83241 CDD

Device

(FDDI Clock Distribution Device)

General Description

The CDD device is a clock generation and distribution de-
vice intended for use in FDDI (Fiber Distributed Data Inter-
face) networks The device provides the complete set of
clocks required to convert byte wide data to serial format for
fiber medium transmission and to move byte wide data be-
tween the PLAYER

and BMAC

devices in various sta-

tion configurations 12 5 MHz and 125 MHz differential ECL
clocks are generated for the conversion of data to serial
format and 12 5 MHz and 25 MHz TTL clocks are generated
for the byte wide data transfers

Features

Provides 12 5 MHz and 25 MHz TTL clocks

12 5 MHz and 125 MHz ECL clocks

5 phase TTL local byte clocks eliminate clock
skew problems in concentrators

Internal VCO requires no varactors coils or
adjustments

Option for use of High Q external VCO

125 MHz clock generated from a 12 5 MHz crystal

External PLL synchronizing reference for
concentrator configurations

28-pin PLCC package

BiCMOS processing

TL F 10385 � 1

FIGURE 1-1 FDDI Chip Set Block Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corporation

BMAC

BSI

CDD

CRD

and PLAYER

are trademarks of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

1 0 FDDI Chip Set Overview

National Semiconductor's FDDI chip set consists of five
components as shown in

Figure 1-1 For more information

about the other devices in the chip set consult the appropri-
ate data sheets and application notes

DP83231 CRD

Device

Clock Recovery Device

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream

Features

PHY Layer loopback test

Crystal controlled

Clock locks in less than 85 ms

DP83241 CDD

Device

Clock Distribution Device

From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices

DP83251 55 PLAYER

Device

Physical Layer Controller

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard

Features

4B 5B encoders and decoders

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detector generator

Link error detector

Configuration switch

Full duplex operation

Separate management port that is used to configure and
control operation

addition

the

DP83255

contains

additional

PHY

Data request and PHY

Data indicate port required

for concentration and dual attach stations

DP83261 BMAC

Device

Media Access Controller

The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard

Features

All of the standard defined ring service options

Full duplex operation with through parity

Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )

Supports Individual Group Short Long and External
Addressing

Generates Beacon Claim and Void frames internally

Extensive ring and station statistics gathering

Extensions for MAC level bridging

Separate management port that is used to configure and
control operation

Multi-frame streaming interface

DP83265 BSI

Device

System Interface

The BSI Device implements an interface between the Na-
tional FDDI BMAC device and a host system

Features

32-bit wide Address Data path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit words

Interfaces to low-cost DRAMs or directly to system bus

Provides 2 Output and 3 Input Channels

Supports Header Info splitting

Efficient data structures

Programmable Big or Little Endian alignment

Full Duplex data path allows transmission to self

Comfirmation status batching services

Receive frame filtering services

Operates from 12 5 MHz to 25 MHz synchronously with
host system

2 0 Functional Description

The CDD device clocks are all generated from and phase
aligned to either a 12 5 MHz crystal oscillator or a TTL input
reference source using digital phase locked loop tech-
niques The architecture of the Clock Distribution Device en-
sures that the output clocks which are generated have fre-
quency tolerances identical to the 50 PPM crystal reference
When the reference input signal is a backplane signal the
matching of the phase comparator input path delays guar-
antees phase alignment within 3 ns

The phase locked loop generates the desired clocks as
shown in the device Block Diagram One of the Local Byte
Clock (LBC) phases is connected to the FEEDBK IN input of
the phase comparator where its phase and frequency are
compared against that of the selected input reference sig-
nal Any phase error between these signals results in a cor-
rection of the voltage into the Voltage Controlled Oscillator
(VCO) which is proportional to the amount of phase error
The correction voltage tends to drive the frequency of the
VCO in the direction which when divided down minimizes
the LBC to reference signal phase difference When the
phase transition of the LBC occurs before that of the refer-
ence input the VCO frequency is sensed as being too fast
and produces a negative going correction to the VCO input
This in turn slows down the VCO's frequency and delays the
subsequent LBC phase transitions

The device's differential 125 MHz ECL transmit clock and
differential 12 5 MHz ECL load strobe are used by the
PLAYER device to convert data from byte wide NRZ format
to serial NRZI format for fiber medium transmission A
12 5 MHz TTL local byte clock is provided for use by the
PLAYER and the BMAC devices Five phases of the local
byte clock are provided for use in large multi-board concen-
trator configurations to aid in cancelling out backplane de-
lays A 25 MHz Local Symbol Clock (LSC) is provided which
is in phase with the local byte clocks and has a 40% HIGH
and 60% LOW duty cycle

The device provides three user-selectable features The
REF SEL input provides the option to lock the device's out-
puts to a crystal oscillator or to an external TTL signal (REF
IN) The REF IN signal is particularly useful in concentrators
where multiple boards need to be phase locked to a com-

mon reference signal The VCO SEL input provides the op-
tion to use the internally provided VCO or an external LC
voltage controlled oscillator Although the stability of the in-
ternal VCO should be adequate for most applications the
external VCO option provides the means of obtaining the
maximum possible oscillator Q The PHASE SEL input pin
provides the option of selecting whether the five phase LBC
outputs are phase offset 36 degrees or 72 degrees (8 ns or
16 ns)

The phase locked loop (PLL) elements with the exception
of the loop filter which consist of two capacitors and a resis-
tor are fully contained within the device The internal VCO
associated with the PLL has been implemented totally with-
in the device and requires no external LC oscillator tank
coils capacitors or varactors The external VCO option
does provide a means of using these conventional LC oscil-
lator techniques if desired

Connection Diagram

28-Pin PLCC Package

TL F 10385 � 25

Order Number DP83241BV

See NS Package Number V28A

FIGURE 2-1 DP83241 Pinout

Block Diagram

TL F 10385 � 3

FIGURE 2-2 DP83241 Block Diagram

3 0 Pin Descriptions

Symbol

I O

Description

Digital V

Positive power supply for all the internal circuitry intended for operation at 5V

5% relative

to GND A bypass capacitor should be placed as close as possible across the DV

and DGND pins

EXTV

External V

Positive power supply for all the output buffers intended for operation at 5V

5% relative

to GND A bypass capacitor should be placed as close as possible across the EXTV

and EXTGND

pins

DGND

Digital Ground

Internal circuit power supply return

EXTGND

External Ground

Output buffer power supply return

AGND

Analog Ground

Substrate ground used to ensure proper device biasing and isolation

Analog V

Positive power supply for the critical analog circuitry intended for

5V operation

relative to Ground A bypass cap should be placed as close as possible between AV

and AGND

XTL IN

External Crystal Oscillator Input

XTL IN can also be used as a CMOS compatible reference frequency

input for the PLL This input is selected when REF SEL is at a logical LOW level The component
connections required for oscillator operation are shown in the application diagrams

XTL OUT

External Crystal Oscillator Output

XTL OUT is not intended for use as a logic drive output pin

REF IN

Reference Input

TTL compatible input for use as the PLL's phase comparator reference frequency

input when the REF SEL is at a logic HI level This input is for use in concentrator configurations where
there are multiple CDD devices at a given site requiring synchronization

FEEDBK IN

Feedback Input

TTL compatible input for use as the PLL's phase comparator feedback input to close

the loop This input is intended to be driven from one of the LBCs (Local Byte Clocks) This input is
designed to provide the same frequency and within 2 ns of the same phase as REF IN when REF IN is in
active operation

REF SEL

Reference Select

TTL compatible input which selects either the crystal oscillator inputs XTL IN and

XTL OUT or the REF IN inputs as the reference frequency inputs for the PLL The crystal oscillator inputs
are selected when REF SEL is at a logic LOW level and the REF IN input is selected as the reference
frequency when REF SEL is at a logic HI level

FILTER

Filter

Low pass PLL loop filter pin A three element filter consisting of one capacitor in parallel with a

resistor and another capacitor should be connected between this pin and ground

VCO SEL

VCO Select

TTL compatible input used to select either the internal VCO or an external VCO through the

XVCO IN and XVCO INB pins The internal VCO is selected when the VCO SEL pin is at a logic HIGH
level and the external VCO is selected when at a logic LOW level

XVCO IN

External VCO Inputs

Differential inputs for use with an external VCO These inputs are D C biased to

approximately one half V

and can be connected to either a full differential VCO or a single-ended

XVCO INB

VCO To use a single-ended VCO couple the signal into one of the inputs through a series low value
capacitor and bypass the other input to GND through a 0 01 mF capacitor When not in use ground one
input and let the other float

Электронный компонент: DP83241BV