TL F 11708
DP8325656-AP57
PLAYER
a
Device
(FDDI
Physical
Layer
Controller)
PRELIMINARY
October 1994
DP83256 56-AP 57
PLAYER
a
TM
Device (FDDI Physical Layer Controller)
General Description
The DP83256 56-AP 57 Enhanced Physical Layer Control-
ler (PLAYER
a
device) implements one complete Physical
Layer (PHY) entity as defined by the Fiber Distributed Data
Interface (FDDI) ANSI X3T9 5 standard
The PLAYER
a
device integrates state of the art digital
clock recovery and improved clock generation functions to
enhance performance eliminate external components and
remove critical layout requirements
FDDI Station Management (SMT) is aided by Link Error
Monitoring support Noise Event Timer (TNE) support Op-
tional Auto Scrubbing support an integrated configuration
switch and built-in functionality designed to remove all strin-
gent response time requirements such as PC
React and
CF
React
Features
Y
Single chip FDDI Physical Layer (PHY) solution
Y
Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range
Y
Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference
Y
Alternate PMD Interface (DP83256-AP 57) supports
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
Y
No External Filter Components
Y
Connection Management (CMT) Support (LEM TNE
PC
React CF
React Auto Scrubbing)
Y
Full on-chip configuration switch
Y
Low Power CMOS-BIPOLAR design using a single 5V
supply
Y
Full duplex operation with through parity
Y
Separate management interface (Control Bus)
Y
Selectable Parity on PHY-MAC Interface and Control
Bus Interface
Y
Two levels of on-chip loopback
Y
4B 5B encoder decoder
Y
Framing logic
Y
Elasticity Buffer Repeat Filter and Smoother
Y
Line state detector generator
Y
Supports single attach stations
dual attach stations
and concentrators with no external logic
Y
DP83256 for SAS DAS single path stations
Y
DP83257 for SAS DAS single dual path stations
Y
DP83256-AP for SAS DAS single path stations that re-
quire the alternate PMD interface
TL F 11708 1
FIGURE 1-1 FDDI Chip Set Overview
TRI-STATE
is a registered trademark of National Semiconductor Corporation
BMAC
TM
BSI
TM
CDD
TM
CDL
TM
CRD
TM
CYCLONE
TM
MACSI
TM
PLAYER
TM
PLAYERa
TM
and TWISTER
TM
are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Table of Contents
1 0 FDDI CHIP SET OVERVIEW
1 1 FDDI 2-Chip Set
1 2 FDDI TP-PMD Solutions
2 0 ARCHITECTURE DESCRIPTION
2 1 Block Overview
2 2 Interfaces
3 0 FUNCTIONAL DESCRIPTION
3 1 Clock Recovery Module
3 2 Receiver Block
3 3 Transmitter Block
3 4 Configuration Switch
3 5 Clock Generation Module
3 6 Station Management Support
3 7 PHY-MAC Interface
3 8 PMD Interface
4 0 MODES OF OPERATION
4 1 Run Mode
4 2 Stop Mode
4 3 Loopback Mode
4 4 Device Reset
4 5 Cascade Mode
5 0 REGISTERS
5 1 Mode Register (MR)
5 2 Configuration Register (CR)
5 3 Interrupt Condition Register (ICR)
5 4 Interrupt Condition Mask Register (ICMR)
5 5 Current Transmit State Register (CTSR)
5 6 Injection Threshold Register (IJTR)
5 7 Injection Symbol Register A (ISRA)
5 8 Injection Symbol Register B (ISRB)
5 9 Current Receive State Register (CRSR)
5 10 Receive Condition Register A (RCRA)
5 11 Receive Condition Register B (RCRB)
5 12 Receive Condition Mask Register A (RCMRA)
5 13 Receive Condition Mask Register B (RCMRB)
5 14 Noise Threshold Register (NTR)
5 15 Noise Prescale Threshold Register (NPTR)
5 16 Current Noise Count Register (CNCR)
5 17 Current Noise Prescale Count Register (CNPCR)
5 18 State Threshold Register (STR)
5 19 State Prescale Threshold Register (SPTR)
5 20 Current State Count Register (CSCR)
5 21 Current State Prescale Count Register (CSPCR)
5 22 Link Error Threshold Register (LETR)
5 23 Current Link Error Count Register (CLECR)
5 24 User Definable Register (UDR)
5 25 Device ID Register (DIR)
5 26 Current Injection Count Register (CIJCR)
5 27 Interrupt Condition Comparison Register (ICCR)
5 28 Current
Transmit
State
Comparison
Register
(CTSCR)
5 29 Receive Condition Comparison Register A (RCCRA)
5 30 Receive Condition Comparision Register B (RCCRB)
5 31 Mode Register 2 (MODE2)
5 32 CMT Condition Comparison Register (CMTCCR)
5 33 CMT Condition Register (CMTCR)
5 34 CMT Condition Mask Register (CMTCMR)
5 35 Reserved Registers 22H-23H (RR22H-RR23H)
5 36 Scrub Timer Threshold Register (STTR)
5 37 Scrub Timer Value Register (STVR)
5 38 Trigger Definition Register (TDR)
5 39 Trigger Transition Configuration Register (TTCR)
5 40 Reserved Registers 28H-3AH (RR28H-RR3AH)
5 41 Clock Generation Module Register (CGMREG)
5 42 Alternate PMD Register (APMDREG)
5 43 Gain Register (GAINREG)
5 44 Reserved Registers 3EH-3FH (RR3EH-RR3FH)
6 0 SIGNAL DESCRIPTIONS
6 1 DP83256VF Signal Descriptions
6 2 DP83256VF-AP Signal Descriptions
6 3 DP83257VF Signal Descriptions
7 0 ELECTRICAL CHARACTERISTICS
7 1 Absolute Maximum Ratings
7 2 Recommended Operating Conditions
7 3 DC Electrical Characteristics
7 4 AC Electrical Characteristics
8 0 CONNECTION DIAGRAMS
8 1 DP83256VF Connection Diagram Pin Descriptions
8 2 DP83256VF-AP Connection Diagram Pin Descrip-
tions
8 3 DP83257VF Connection Diagram Pin Descriptions
9 0 PACKAGE INFORMATION
9 1 Land Patterns
9 2 Mechanical Drawings
2
1 0 FDDI Chip Set Overview
National Semiconductor's next generation FDDI 2-chip set
consists of two components as shown in
Figure 1-1 The
PLAYER
a
device integrates the features of the DP83231
CRD
TM
Clock Recovery Device DP83241 CDD
TM
Clock
Distribution Device and DP83251 55 PLAYER
TM
Physical
Layer Controller In addition the PLAYER
a
device contains
enhanced SMT support
National Semiconductor's FDDI TP-PMD Solutions consist
of two components
the DP83222 CYCLONE
TM
Twisted
Pair FDDI Stream Cipher Device and the DP83223A
TWISTER
TM
Twisted Pair FDDI Transceiver Device
For more information on the other devices of the chip set
consult the appropriate datasheets and application notes
1 1 FDDI 2-CHIP SET
DP83256 56-AP 57 PLAYER
a
Device Physical Layer Controller
The PLAYER
a
device implements the Physical Layer
(PHY) protocol as defined by the ANSI FDDI PHY X3T9 5
standard
Features
Y
Single chip FDDI Physical Layer (PHY) solution
Y
Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range
Y
Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference
Y
Alternate PMD Interface (DP83256-AP 57) supports
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
Y
No External Filter Components
Y
Connection Management (CMT) Support (LEM TNE
PC
React CF
React Auto Scrubbing)
Y
Full on-chip configuration switch
Y
Low Power CMOS-BIPOLAR design using a single 5V
supply
Y
Full duplex operation with through parity
Y
Separate management interface (Control Bus)
Y
Selectable Parity on PHY-MAC Interface and Control
Bus Interface
Y
Two levels of on-chip loopback
Y
4B 5B encoder decoder
Y
Framing logic
Y
Elasticity Buffer Repeat Filter and Smoother
Y
Line state detector generator
Y
Supports single attach stations
dual attach stations
and concentrators with no external logic
Y
DP83256 56-AP for SAS DAS single path stations
Y
P83257 for SAS DAS single dual path stations
In addition the DP83257 contains the additional PHY
Da-
ta request and PHY
Data indicate ports required for con-
centrators and dual attach dual path stations
DP83266 MACSI
TM
Device Media
Access Controller and System
Interface
The DP83266 Media Access Controller and System Inter-
face (MACSI) implements the ANSI X3T9 5 Standard Media
Access Control (MAC) protocol for operation in an FDDI
token ring and provides a comprehensive System Interface
The MACSI device transmits receives repeats and strips
tokens and frames It produces and consumes optimized
data structures for efficient data transfer Full duplex archi-
tecture with through parity allows diagnostic transmission
and self testing for error isolation in point-to-point connec-
tions
The MACSI device includes the functionality of both the
DP83261 BMAC device and the DP83265 BSI-2 device with
additional enhancements for higher performance and reli-
ability
Features
Y
Over 9 Kbytes of on-chip FIFO
Y
5 DMA Channels (2 Output and 3 Input)
Y
12 5 MHz to 33 MHz operation
Y
Full duplex operation with through parity
Y
Real-time VOID frame stripping indicator for bridges
Y
On-chip Address bit swapping capability
Y
32-bit wide Address Data path with byte parity
Y
Programmable transfer burst sizes of 4 or 8 32-bit
words
Y
Receive frame filtering services
Y
Frame-per-Page mode controllable on each DMA
channel
Y
Demultiplexed Addresses supported on ABus
Y
New multicast address matching
Y
ANSI X3T9 5 MAC standard defined ring service op-
tions
Y
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Y
Supports Individual Group Short Long and External
Addressing
Y
Generates Beacon Claim and Void frames
Y
Extensive ring and station statistics gathering
Y
Extension for MAC level bridging
Y
Enhanced SBus compatibility
Y
Interfaces to DRAMs or directly to system bus
Y
Supports frame Header Info splitting
Y
Programmable Big or Little Endian alignment
3
DP83222 CYCLONE Twisted Pair
FDDI Stream Cipher Device
General Description
The DP83222 CYCLONE Stream Cipher Scrambler Des-
crambler Device is an integrated circuit designed to inter-
face directly with the serial bit streams of a Twisted Pair
FDDI PMD The DP83222 is designed to be fully compatible
with the National Semiconductor FDDI Chip Sets including
twisted pair FDDI Transceivers such as the DP83223A
Twisted Pair Transceiver (TWISTER) The DP83222 re-
quires a 125 MHz Transmit Clock and corresponding Re-
ceive Clock for synchronous data scrambling and descram-
bling The DP83222 is compliant with the ANSI X3T9 5
TP-PMD standard and is required for the reduction of EMI
emission over unshielded media The DP83222 is specified
to work in conjunction with existing twisted pair transceiver
signalling schemes and enables high bandwidth transmis-
sion over Twisted Pair copper media
Features
Y
Enables 100 Mbps FDDI signalling over Category 5
Unshielded Twisted Pair (UTP) cable and Type 1
Shielded Twisted Pair (STP)
Y
Reduces EMI emissions over Twisted Pair media
Y
Compatible with ANSI X3T9 5 TP-PMD standard
Y
Requires a single
a
5V supply
Y
Transparent mode of operation
Y
Flexible NRZ and NRZI format options
Y
Advanced BiCMOS process
Y
Signal Detect and Clock Detect inputs provided for en-
hanced functionality
Y
Suitable for Fiber Optic PMD replacement applications
DP83223A TWISTER High Speed
Networking Transceiver Device
General Description
The DP83223A Twisted Pair Transceiver is an integrated
circuit capable of driving and receiving either binary or
(MLT-3) encoded datastreams The DP83223A Transceiver
is designed to interface directly with standards compliant
FDDI 100BASE-TX or STS-3c ATM chip sets allowing low
cost data links over copper based media The DP83223A
allows links of up to 100 meters over both Shielded Twisted
Pair (STP) and datagrade Unshielded Twisted Pair (UTP) or
equivalent The electrical performance of the DP83223A
meets or exceeds all performance parameters specified
in the ANSI X3T9 5 TP-PMD standard the IEEE 802 3
100BASE-TX Fast Ethernet Specification and the ATM Fo-
rum 155 Mbps Twisted Pair PMD Interface Specification
The DP83223A also provides important features such as
baseline restoration TRI-STATE
capable transmit outputs
and controlled transmit output edge rates (to reduce EMI
radiation) for both binary and MLT-3 modes of operation
Features
Y
Compliant with ANSI X3T9 5 TP-PMD standard
Y
Compliant with IEEE 802 3 100BASE-TX Ethernet draft
standard
Y
Compliant with ATM Forum 155 Mbps Twisted Pair
Specification
Y
Integrated baseline restoration circuit
Y
Integrated transmitter and receiver with adaptive equali-
zation circuit
Y
Programmable binary or MLT-3 operation
Y
Isolated TX and RX power supplies for minimum noise
coupling
Y
Controlled transmit output edge rates for reduced EMI
Y
TRI-STATE capable current transmit outputs
Y
Loopback feature for board diagnostics
Y
Programmable transmit voltage amplitude
4
2 0 Architecture Description
2 1 BLOCK OVERVIEW
The PLAYER
a
device is comprised of six blocks Clock
Recovery Receiver Configuration Switch Transmitter Sta-
tion Management (SMT) Support and Clock Generation
Module as shown in
Figure 2-1
Clock Recovery
The Clock Recovery Module accepts a 125 Mbps NRZI data
stream from the external PMD receiver It then provides the
extracted and synchronized data and clock to the Receiver
block
The Clock Recovery Module performs the following opera-
tions
Locks to and tracks the incoming NRZI data stream
Extracts data stream and synchronized 125 MHz clock
Receiver
During normal operation the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Re-
covery Module During the Internal Loopback mode of oper-
ation the Receiver Block accepts data directly from the
Transmitter Block
The Receiver Block performs the following operations
Optionally converts the incoming data stream from NRZI
to NRZ
Decodes the data from 5B to 4B coding
Converts the serial bit stream into 10-bit bytes composed
of 8 bits data 1 bit parity and 1 bit control information
Compensates for the differences between the upstream
station clock and the local clocks
Decodes Line States
Detects link errors
Presents data symbol pairs (bytes) to the Configuration
Switch Block
Configuration Switch
An FDDI station may be in one of three configurations Iso-
late Wrap or Thru The Configuration Switch supports these
configurations by switching the transmitted and received
data paths between PLAYER
a
devices and one or more
MACSI devices
The configuration switch is integrated into the PLAYER
a
device therefore no external logic is required for this func-
tion
Setting the Configuration switch can be done explicitly via
the Control Bus Interface or it can be set automatically with
the CF
React SMT Support feature
TL F 11708 2
FIGURE 2-1 PLAYER
a
Device Block Diagram
5
PDF 
ZIP