TL F 9336

DP8344B

Biphase

Communications

ProcessorBCP

November 1991

DP8344B Biphase Communications Processor

BCP

General Description

The DP8344B BCP is a communications processor de-
signed to efficiently process IBM

3270 3299 and 5250

communications protocols A general purpose 8-bit protocol
is also supported

The BCP integrates a 20 MHz 8-bit Harvard architecture
RISC processor and an intelligent software-configurable
transceiver on the same low power microCMOS chip The
transceiver is capable of operating without significant proc-
essor interaction releasing processor power for other tasks
Fast and flexible interrupt and subroutine capabilities with
on-chip stacks make this power readily available

The transceiver is mapped into the processor's register
space communicating with the processor via an asynchro-
nous interface which enables both sections of the chip to
run from different clock sources The transmitter and receiv-
er run at the same basic clock frequency although the re-
ceiver extracts a clock from the incoming data stream to
ensure timing accuracy

The BCP is designed to stand alone and is capable of imple-
menting a complete communications interface using the
processor's spare power to control the complete system
Alternatively the BCP can be interfaced to another proces-
sor with an on-chip interface controller arbitrating access to
data memory Access to program memory is also possible
providing the ability to download BCP code

A simple line interface connects the BCP to the communica-
tions line The receiver includes an on-chip analog compar-
ator suitable for use in a transformer-coupled environment

although a TTL-level serial input is also provided for applica-
tions where an external comparator is preferred

A typical system is shown below Both coax and twinax line
interfaces are shown as well as an example of the (option-
al) remote processor interface

Features

Transceiver

Software configurable for 3270 3299 5250 and general
8-bit protocols

Fully registered status and control

On-chip analog line receiver

Processor

20 MHz clock (50 ns T-states)

Max instruction cycle 200 ns

33 instruction types (50 total opcodes)

ALU and barrel shifter

64k x 8 data memory address range

64k x 16 program memory address range
(note typical system requires

2k program memory)

Programmable wait states

Soft-loadable program memory

Interrupt and subroutine capability

Stand alone or host operation

Flexible bus interface with on-chip arbitration logic

General

Low power microCMOS typ I

25 mA at 20 MHz

84-pin plastic leaded chip carrier (PLCC) package

Block Diagram

Typical BCP System

TL F 9336 � 51

FIGURE 1

BCP

and TRI-STATE

are registered trademarks of National Semiconductor Corporation

IBM

is a registered trademark of International Business Machines Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

The DP8344B is an enhanced version of the DP8344A exhibiting improved switching performance and additional
functionality The device has been been characterized in a number of applications and found to be a compatible
replacement for the DP8344A Differences between the DP8344A and DP8344B are noted by shading of the text on the
pages of this data sheet For more information refer to Section 6 6

Note

In this document XXX denotes a control or status bit in a register

YYY denotes a register

Table of Contents

1 0 COMMUNICATIONS PROCESSOR OVERVIEW

1 1 Communications Protocols

1 2 Internal Architecture Overview

1 3 Timing Overview

1 4 Data Flow

1 5 Remote Interface Overview

2 0 CPU DESCRIPTION

2 1 CPU Architectural Description

2 1 1 Register Set

2 1 1 1 Banked Registers

2 1 1 2 Timing Control Registers

2 1 1 3 Interrupt Control Registers

2 1 1 4 Timer Registers

2 1 1 5 Transceiver Registers

2 1 1 6 Condition Code Remote Handshaking

2 1 1 7 Index Registers

2 1 1 8 Stack Registers

2 1 2 Timer

2 1 2 1 Timer Operation

2 1 3 Instruction Set

2 1 3 1 Harvard Architecture Implications

2 1 3 2 Addressing Modes

2 1 3 3 Instruction Set Overview

2 2 Functional Description

2 2 1 ALU

2 2 2 Timing

2 2 3 Interrupts

2 2 4 Oscillator

3 0 TRANSCEIVER

3 1 Transceiver Architectural Description

3 1 1 Protocols

3 1 1 1 IBM 3270

3 1 1 2 IBM 3299

3 1 1 3 IBM 5250

3 1 1 4 General Purpose 8-Bit

3 2 Transceiver Functional Description

3 2 1 Transmitter

3 2 2 Receiver

3 2 3 Transceiver Interrupts

3 2 4 Protocol Modes

3 2 5 Line Interface

3 2 5 1 3270 Line Interface

3 2 5 2 5250 Line Interface

4 0 REMOTE INTERFACE AND ARBITRATION SYSTEM

(RIAS)

4 1 RIAS Architectural Description

4 1 1 Remote Arbitration Phases

4 1 2 Access Types

4 1 3 Interface Modes

4 1 4 Execution Control

4 2 RIAS Functional Description

4 2 1 Buffered Read

4 2 2 Latched Read

4 2 3 Slow Buffered Write

4 2 4 Fast Buffered Write

4 2 5 Latched Write

4 2 6 Remote Rest Time

Table of Contents

(Continued)

5 0 DEVICE SPECIFICATIONS

5 1 Pin Description

5 1 1 Timing Control Signals

5 1 2 Instruction Memory Interface

5 1 3 Data Memory Interface

5 1 4 Transceiver Interface

5 1 5 Remote Interface

5 1 6 External Interrupts

5 2 Absolute Maximum Ratings

5 3 Operating Conditions

5 4 Electrical Characteristics

5 5 Switching Characteristics

5 5 1 Definitions

5 5 2 Timing Tables and Figures

6 0 REFERENCE SECTION

6 1 Instruction Set Reference

6 2 Register Set Reference

6 2 1 Bit Index

6 2 2 Register Description

6 2 3 Bit Definition Tables

6 2 3 1 Processor

6 2 3 2 Transceiver

6 3 Remote Interface Reference

6 4 Development Tools

6 4 1 Assembler System

6 4 2 Development Kit

6 4 3 Multi-Protocol Adapter Design Evaluation Kit

6 4 4 Inverse Assembler

6 5 3rd Party Suppliers

6 5 1 Crystal

6 5 2 System Development Tools

6 6 DP8344A Compatibility Guide

6 6 1 CPU Timing Changes

6 6 2 Additional Functionality

6 6 2 1 4 T-state Read

6 6 2 2 A AD Reset State

6 6 2 3 RIC

6 6 2 4 Transceiver

6 7 Reported Bugs

6 7 1 History

6 7 2 LJMP LCALL Address Decode

6 7 2 1 Suggested Work-around

6 8 Glossary

6 9 Physical Dimensions

List of Illustrations

Block Diagram of Typical BCP System

Biphase Encoding

1-1

IBM 3270 Message Format

1-2

Simplified Block Diagram

1-3

Memory Configuration

1-4

Effect of Memory Wait States on Timing

1-5

1-6a

Data Memory WRITE Data Flow

1-6b

Data Memory READ Data Flow

1-6c

WRITE to Transmitter Data Flow

1-6d

READ from Receiver Data Flow

1-6e

Load Immediate Data Data Flow

1-6f

Basic Remote Interface

1-7

2-1

Timer Block Diagram

2-2

Timer Interrupt Diagram

2-3

Index Register Map

2-4

Coding Examples of Equivalent Conditional Jump Instructions

2-5

JRMK Instruction Example

2-6

Condition Code Register ALU Flags

2-7

Carry and Overflow Calculations

2-8

Shifts' Effect on Carry

2-9

Rotates' Effect on Carry

2-10

Multi-Byte Arithmetic Instruction Sequences

2-11

CPU-CLK Synchronization with X1

2-12

Changing from OCLK 2 to OCLK

2-13

Two T-state Instruction

2-14

Three T-state Instruction

2-15

Three T-state Data Memory Write Instruction

2-16

Three T-state Data Memory Read Instruction

2-17

Four T-state Data Memory Read Instruction

2-18

Four T-state Program Control Instruction

2-19

Four T-state Two Word Instruction

2-20

Data Memory Write with One Wait State

2-21

Data Memory Read with One Wait State

2-22

Data Memory Read with Two Wait States

2-23

Two T-state Instruction with Two Wait States

2-24

Four T-state Instruction with One Wait State

2-25

Data Memory Access Wait Timing

2-26

Two T-state Instruction WAIT Timing

2-27

Three T-state Program Control Instruction WAIT Timing

2-28

Four T-state Program Control Instruction WAIT Timing

2-29

LOCK Timing

2-30

LOCK Timing with One Wait State

2-31

CPU Start-Up Timing

2-32

Functional State Diagram of CPU Timing

2-33

Interrupt Timing

2-34

DP8344B Operation with Crystal

2-35

DP8344B Operation with External Clock

2-36

List of Illustrations

(Continued)

System Block Diagram Showing Details of Line Interface

3-1

Biphase Encoding

3-2

3270 3299 Protocol Framing Format

3-3

5250 Protocol Framing Format

3-4

General Purpose 8-Bit Protocol Framing Format

3-5

Block Diagram of Transceiver Showing CPU Interface

3-6

Transmitter Output

3-7

Timing of Receiver Flags Relative to Incoming Data

3-8

3270 3299 Frame Assembly Disassembly Description

3-9

5250 Frame Assembly Disassembly Description

3-10

General Purpose 8-Bit Frame Assembly Disassembly Description

3-11

BCP Receiver Design

3-12

BCP Driver Design

3-13

BCP Coax Twisted Pair Front End

3-14

5250 Line Interface Schematic

3-15

Remote Interface Processor

4-1

Remote Interface Control Register

4-2

Generic Remote Access

4-3

Generic RIC Access

4-4

Memory Select Bits in RIC

4-5

Generic DMEM Access

4-6

Generic PC Access

4-7

Generic IMEM Access

4-8

Read from Remote Processor

4-9

Buffered Write from Remote Processor

4-10

Latched Write from Remote Processor

4-11

Minimum BCP Remote Processor Interface

4-12

Interface Mode Bits

4-13

Flow Chart of Buffered Read Mode

4-14

Buffered Read of Data Memory by Remote Processor

4-15

Flow Chart of Latched Read Mode

4-16

Latched Read of Data Memory by Remote Processor

4-17

Flow Chart of Slow Buffered Write Mode

4-18

Slow Buffered Write to Data Memory by Remote Processor

4-19

Flow Chart of Fast Buffered Write Mode

4-20

Fast Buffered Write to Data Memory by Remote Processor

4-21

Flow Chart of Latched Write Mode

4-22

Latched Write to Data Memory by Remote Processor

4-23

Mistaking Two Remote Accesses as Only One

4-24

Remote Rest Time for All Modes Except Latched Write

4-25

Rest Time for Latched Write Mode

4-26

DP8344B Top View

5-1

Switching Characteristic Measurement Waveforms

5-2

Data Memory Read Timing

5-3

Data Memory Write Timing

5-4

Instruction Memory Timing

5-5

Clock Timing

5-6

Электронный компонент: DP8344