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2002 National Semiconductor Corporation

www.national.com

September 2002

DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access
Controller and Physical Layer (MacPhyter

)

General Description

DP83815 is a single-chip 10/100 Mb/s Ethernet Controller
for the PCI bus. It is targeted at low-cost, high volume PC
mother boards, adapter cards, and embedded systems.
The DP83815 fully implements the V2.2 33 MHz PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83815 can support full duplex 10/100 Mb/s transmission
and reception, with minimum interframe gap.

The DP83815 device is an integration of an enhanced
version of the National Semiconductor PCI MAC/BIU
(Media Access Controller/Bus Interface Unit) and a 3.3V
CMOS physical layer interface.

Features

-- IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports

traditional data rates of 10 Mb/s Ethernet and 100 Mb/s
Fast Ethernet (via internal phy)

-- Bus master - burst sizes of up to 128 dwords (512 bytes)

-- BIU compliant with PC 97 and PC 98 Hardware Design

Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1.1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a

-- Wake on LAN (WOL) support compliant with PC98,

PC99, SecureOn, and OnNow, including directed
packets, Magic Packet

, VLAN packets, ARP packets,

pattern match packets, and Phy status change

-- Clkrun function for PCI Mobile Design Guide

-- Virtual LAN (VLAN) and long frame support

-- Support for IEEE 802.3x Full duplex flow control

-- Extremely flexible Rx packet filtration including: single

address perfect filter with MSb masking, broadcast, 512
entry multicast/unicast hash table, deep packet pattern
matching for up to 4 unique patterns

-- Statistics gathered for support of RFC 1213 (MIB II),

RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management

-- Internal 2 KB Transmit and 2 KB Receive data FIFOs

-- Serial EEPROM port with auto-load of configuration data

from EEPROM at power-on

-- Flash/PROM interface for remote boot support

-- Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical

layer

-- IEEE 802.3 10BASE-T transceiver with integrated filters

-- IEEE 802.3u 100BASE-TX transceiver

-- Fully integrated ANSI X3.263 compliant TP-PMD

physical sublayer with adaptive equalization and
Baseline Wander compensation

-- IEEE 802.3u Auto-Negotiation - advertised features

configurable via EEPROM

-- Full Duplex support for 10 and 100 Mb/s data rates

-- Single 25 MHz reference clock

-- 144-pin LQFP and 160-pin LBGA packages

-- Low power 3.3V CMOS design with typical consumption

of 561 mW operating, 380 mW during WOL mode, 33
mW sleep mode

-- IEEE 802.3u MII for connecting alternative external

Physical Layer Devices

System Diagram

PCI Bus

DP83815

EEPROM

Isolation

10/100 Twisted Pair

BIOS ROM

(optional) (optional)

TRI-STATE

�

is a registered trademark of National Semiconductor Corporation.

Magic Packet

is a trademark of Advanced Micro Devices, Inc.

www.national.com

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Table of Contents

1.0

Connection Diagram . . . . . . . . . . . . . . . . . . 4

1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4
1.2 160 pin LBGA Package (UJB) . . . . . . . . . . 5

2.0

Pin Description . . . . . . . . . . . . . . . . . . . . . . 6

3.0

Functional Description . . . . . . . . . . . . . . . 13

3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.1 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 Tx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 Rx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Buffer Management . . . . . . . . . . . . . . . . . 15

3.2.1 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.3 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.4 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Interface Definitions . . . . . . . . . . . . . . . . . 16

3.3.1 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 18

3.4.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.2 Auto-Negotiation Register Control . . . . . . . . . . . . . 18
3.4.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . 18
3.4.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . 19
3.4.5 Enabling Auto-Negotiation via Software . . . . . . . . 19
3.4.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . 19

3.5 LED Interfaces . . . . . . . . . . . . . . . . . . . . . 19
3.6 Half Duplex vs. Full Duplex . . . . . . . . . . . 20
3.7 Phy Loopback . . . . . . . . . . . . . . . . . . . . . 20
3.8 Status Information . . . . . . . . . . . . . . . . . . 20
3.9 100BASE-TX TRANSMITTER . . . . . . . . . 20

3.9.1 Code-group Encoding and Injection . . . . . . . . . . . 21
3.9.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . 22
3.9.4 Binary to MLT-3 Convertor / Common Driver . . . . 22

3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 23

3.10.1 Input and Base Line Wander Compensation . . . . 23
3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . . 25
3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . 26
3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . 26
3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . . 27
3.10.7 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.8 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . . 27
3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . . 27
3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 27

3.11 10BASE-T Transceiver Module . . . . . . . . 28

3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.3 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.4 Normal Link Pulse Detection/Generation . . . . . . . 28
3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11.6 Automatic Link Polarity Detection . . . . . . . . . . . . . 29
3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . . 29
3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . 29
3.11.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 29

3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 29

3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . . 29

3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 29
3.12.3 MII Serial Management Access . . . . . . . . . . . . . 30
3.12.4 Serial Management Access Protocol . . . . . . . . . 30
3.12.5 Nibble-wide MII Data Interface . . . . . . . . . . . . . . 30
3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.0

Register Set . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 Configuration Registers . . . . . . . . . . . . . . 32

4.1.1 Configuration Identification Register . . . . . . . . . . . 32
4.1.2 Configuration Command and Status Register . . . 33
4.1.3 Configuration Revision ID Register . . . . . . . . . . . 34
4.1.4 Configuration Latency Timer Register . . . . . . . . . 35
4.1.5 Configuration I/O Base Address Register . . . . . . . 35
4.1.6 Configuration Memory Address Register . . . . . . . 36
4.1.7 Configuration Subsystem Identification Register . 36
4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 37
4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 37
4.1.10 Configuration Interrupt Select Register . . . . . . . . 38
4.1.11 Power Management Capabilities Register . . . . . 38
4.1.12 Power Management Control and Status Register 39

4.2 Operational Registers . . . . . . . . . . . . . . . 40

4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 Configuration and Media Status Register . . . . . . . 42
4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 44
4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 45
4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 46
4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 47
4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 49
4.2.9 Transmit Descriptor Pointer Register . . . . . . . . . . 49
4.2.10 Transmit Configuration Register . . . . . . . . . . . . . 50
4.2.11 Receive Descriptor Pointer Register . . . . . . . . . . 51
4.2.12 Receive Configuration Register . . . . . . . . . . . . . 52
4.2.13 CLKRUN Control/Status Register . . . . . . . . . . . . 53
4.2.14 Wake Command/Status Register . . . . . . . . . . . . 55
4.2.15 Pause Control/Status Register . . . . . . . . . . . . . . 57
4.2.16 Receive Filter/Match Control Register . . . . . . . . 58
4.2.17 Receive Filter/Match Data Register . . . . . . . . . . 59
4.2.18 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 60
4.2.19 Boot ROM Address Register . . . . . . . . . . . . . . . . 64
4.2.20 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 64
4.2.21 Silicon Revision Register . . . . . . . . . . . . . . . . . . 64
4.2.22 Management Information Base Control Register 65
4.2.23 Management Information Base Registers . . . . . . 66

4.3 Internal PHY Registers . . . . . . . . . . . . . . . 67

4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 67
4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 68
4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 69
4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 69
4.3.5 Auto-Negotiation Advertisement Register . . . . . . 69
4.3.6 Auto-Negotiation Link Partner Ability Register . . . 70
4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 71
4.3.8 Auto-Negotiation Next Page Transmit Register . . 71
4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.10 MII Interrupt Control Register . . . . . . . . . . . . . . . 74
4.3.11 MII Interrupt Status and Misc. Control Register . 74
4.3.12 False Carrier Sense Counter Register . . . . . . . . 75
4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 75
4.3.14 100 Mb/s PCS Configuration and Status Register 75
4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 76
4.3.16 10BASE-T Status/Control Register . . . . . . . . . . . 77

4.4 Recommended Registers Configuration . 78

5.0

Buffer Management . . . . . . . . . . . . . . . . . . 79

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 79

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5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . . 81
5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . 82
5.1.4 Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.2 Transmit Architecture . . . . . . . . . . . . . . . 83

5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 83
5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3 Receive Architecture . . . . . . . . . . . . . . . . 86

5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 86
5.3.2 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.0

Power Management and Wake-On-LAN. . 89

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Definitions (for this document only) . . . . . 89
6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 89
6.4 Power Management . . . . . . . . . . . . . . . . 89

6.4.1 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.2 D1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.3 D2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.4 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.5 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 90

6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 90
6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . 91

6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 91

6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 91

6.7 Pin Configuration for Power Management 91

7.0

DC and AC Specifications . . . . . . . . . . . . . 92

7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 92
7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 93

7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 94
7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 94
7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.7 EEPROM Auto-Load . . . . . . . . . . . . . . . . . . . . . 101
7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 102
7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 103
7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 104
7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 104
7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 105
7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 105
7.2.14 Media Independent Interface (MII . . . . . . . . . . . 106

List of Figures

Figure 3-1

DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-2

MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3-3

Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3-4

DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 3-5

LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3-6

100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3-7

Binary to MLT-3 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 3-8

100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 3-9

100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 3-10

EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . . 26

Figure 3-11

MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 3-12

MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 3-13

MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 3-14

10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 3-15

Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 3-16

Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 4-1

Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 4-2

Hash Table Memory - 40h bytes addressed on word boundaries . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 5-1

Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 5-2

Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 5-3

List and Ring Descriptor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 5-4

Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 5-5

Transmit State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 5-6

Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 5-7

Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

List of Tables

Table 3-1

4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 3-2

Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 4-1

Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4-2

Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 4-3

MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 5-1

DP83815 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-2

cmdsts Common Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-3

Transmit Status Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 5-4

Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 5-5

Transmit State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 5-6

Receive State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 6-1

Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 6-2

PM Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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5

1.0 Connection Diagram

1.1 144 LQFP Package (VNG)

Order Number DP83815DVNG

See NS Package Number VNG144A

121

122

123

124

125

126

127

128

129

130

131

132

Identification

Pin1

37
38
39
40

120
119
118
117
116
115
114
113
112

110
109

111

DEVSE

RDYN

IRDYN

CBEN2

AD1

STO

PERRN

SERRN

PAR

CBEN1

AD1

AD9

PCI

VSS

AD8

AD1

AD2

I
D

SEL

PCI

VSS

PCI

DD3

VSSI

PCI

DD4

VDDIO

PCI

VSS

PCI

DD2

CBEN3

AD26

CBEN0

MACVSS1

MACVDD1

RESERVED

VREF

PCIVDD1

AD29

AD31

PCIVSS1

REQN

GNTN

RSTN

INTAN

AD28

PCICLK

AD30

PMEN/CLKRUNN

TXIOVSS2

TXIOVSS1

TPTDP

TPTDM

RXAVDD2

RXAVSS2

TPRDP

TPRDM

SUBGND2

AD27

AD7

AD6

AD5
PCIVSS5

MA1/LED10N

MA2/LED100N

/
EEDI

/
EECL

MWRN

MD4/EEDO

MD3

EESEL

AD0
AD1
AD2
AD3

AD4

MD0

MCSN

MD1/CFGDISN

MD2

MD5

MD6

MD7

MA0/LEDACTN

PCIVDD5

VSSI

VDDI

MACVSS2

MACVDD2

VDDIO5
VSSIO5

I
O

RXCL

RXD0

RXD1

RXD2

RXD3

RXOE

RXER/

RXDV/M

/
M

CRS

XEN

/
M

VSSI

VDDI

VSSI

VDDI

DP83815

SUBGND3

PHYVSS1

PHYVDD1

3VAUX

67
68
69
70
71
72

100

101

102

103

104

105

106

107

108

144
143
142
141
140
139
138
137
136
135
134
133

RXAVSS1

RXAVDD1

PWRGOOD

MRDN

TXDVDD

FXVDD

FXVSS

PHYVSS2

PHYVDD2

SUBGND1

RESERVED

TXDVSS

Электронный компонент: DP83815VNG