1998 National Semiconductor Corporation
www.national.com
DP83850C 100 Mb/s TX/T4 Repeater Interface Contr
oller (100RIC
TM
)
June 1998
DP83850C 100 Mb/s TX/T4 Repeater Interface Controller
(100RIC
TM
)
General Description
The DP83850C 100 Mb/s TX/T4 Repeater Interface Con-
troller, known as 100RIC, is designed specifically to meet
the needs of today's high speed Ethernet networking sys-
tems. The DP83850C is fully compatible with the IEEE
802.3 repeater's clause 27.
The DP83850C supports up to twelve 100 Mb/s links with
its network interface ports. The 100RIC can be configured
to be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters with up to 372 ports may
be constructed by cascading DP83850Cs together using
the built-in Inter Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83850C based repeater
becomes a managed entity that is compatible with IEEE
802.3u (clause 30), collecting and providing an easy inter-
face to all the required network statistics.
System Diagram
FAST
is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
100RIC
TM
is a trademark of National Semiconductor Corporation.
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
DP83223
100BASE-X
Transceiver
Port 0
100Mb/s
Ethernet
Ports
Inter Repeater Bus
RX Enable [11..0]
Management Bus
MII
DP83850C
100 Mb/s
Repeater Interface Controller
(100RIC8)
Management
I/O Devices
Program
Memory
Management
CPU
Statistics
SRAM
DP83840A
100 PHY
#0
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 2
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 11
DP83840A
100 PHY
#11
(IR_COL, IR_DV)
(TXD[3:0], TX_ER, TX_RDY)
Features
s
IEEE 802.3u repeater and management compatible
s
Supports Class II TX translational repeater and Class I
T4 repeater
s
Supports 12 network connections (ports)
s
Up to 31 repeater chips cascadable for larger hub appli-
cations (up to 372 ports)
s
Separate jabber and partition state machines for each
port
s
Management interface to DP83856 allows all repeater
MIBs to be maintained
s
Large per-port management counters - reduces man-
agement CPU overhead
s
On-chip elasticity buffer for PHY signal re-timing to the
DP83850C clock source
s
Serial register interface - reduces cost
s
Physical layer device control/status access available via
the serial register interface
s
Detects repeater identification errors
s
132 pin PQFP package
2
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Block Diagram
PHY
#0
PHY
#1
PHY
#11
CRS[0]
RXE[0]
TXE[0]
CRS[1]
RXE[1]
TXE[1]
CRS[11]
RXE[11]
TXE[11]
RXD[3:0],RX_ER, RXC, RX_DV
TXD[3:0], TX_ER
CRS[11:0]
SERIAL REGISTER/MANAGEMENT INTERFACE
RDIR
RDIO
BRDC
GRDIO
RDC
/SDV
SERIAL REGISTER
ACCESS LOGIC
REGISTER
MUX
PER PORT
JABBER CONTROL
& AUTO-PARTITION
STATE MACHINES
PER PORT
COL & PART
COUNTERS
LATE EVENT
COUNTERS
SHORT EVENT
COUNTERS
CONFIG./STATUS
REGISTERS
TXE[11:0]
REPEATER
STATE
MACHINE
TXE
CONTROL
EB_ERROR
ELASTICITY
BUFFER
IRD[3:0], /IRD_ER, IRD_CK, /IRD_V
EEPROM
ACCESS LOGIC
EEPROM INTERFACE
EE_DO
EE_DI
EE_CS
EE_CK
Other Registers
SELECT/COL.
DETECT LOGIC
PORT_COL[11:0]
CRS[11:0]
RXE[11:0]
/IR_COL_IN
/IR_COL_OUT
/ACTIVEO
/IR_BUS_EN
IR_VECT[4:0]
PHYSICAL LAYER INTERFACE
DP83850C
100RIC
TX/T4
DISTRIBUTED
ARBITRATION
LOGIC
MANAGEMENT
LOGIC
LCK
/RST
RID_ER
RID[4:0]
State
MD[3:0]
/M_DV
M_CK
/M_ER
MANAGEMENT & INTER REPEATER BUS INTERFACE
Active Port #
ACTIVITY[11:0]
RXD[3:0], RX_ER, RXC, RX_DV
TXD[3:0], TX_ER
TXE[11:0]
RXE[11:0]
CRS[11:0]
TX_RDY
PART[5:0]
IRD_ODIR
Repeater
State Machine
Pre-amble
Regeneration
Jam
Generation
3
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Table of Contents
1.0
Pin Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Physical Layer Interface . . . . . . . . . . . . . . . . . . . . 6
2.2
Inter Repeater and Management Bus Interface . . . 7
2.3
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Pin Type Designation . . . . . . . . . . . . . . . . . . . . . . . 9
3.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Repeater State Machine . . . . . . . . . . . . . . . . . . . 10
3.2
RXE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
TXE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5
Elasticity Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6
Jabber Protection State Machine . . . . . . . . . . . . . 11
3.7
Auto-Partition State Machine . . . . . . . . . . . . . . . . 11
3.8
Inter Repeater Bus Interface . . . . . . . . . . . . . . . . 11
3.9
Management Bus . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.10
Management Event Flags and Counters . . . . . . . 12
3.11
Serial Register Interface . . . . . . . . . . . . . . . . . . . 12
3.12
Jabber/Partition LED Driver Logic . . . . . . . . . . . . 15
3.13
EEPROM Serial Read Access . . . . . . . . . . . . . . . 15
4.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Page 0 Register Map . . . . . . . . . . . . . . . . . . . . . 16
4.2
Page 1 Register Map . . . . . . . . . . . . . . . . . . . . . 17
4.3
Configuration Register (CONFIG) . . . . . . . . . . . 17
4.4
Page Register (PAGE) . . . . . . . . . . . . . . . . . . . . 18
4.5
Partition Status Register (PARTITION) . . . . . . . 18
4.6
Jabber Status Register (JABBER) . . . . . . . . . . . 18
4.7
Administration Register (ADMIN) . . . . . . . . . . . . 19
4.8
Device ID Register (DEVICEID) . . . . . . . . . . . . . 19
4.9
Hub ID 0 Register (HUBID0) . . . . . . . . . . . . . . . 19
4.10
Hub ID 1 Register (HUBID1) . . . . . . . . . . . . . . . 20
4.11
Port Management Counter Registers . . . . . . . . . 20
4.12
Silicon Revision Register (SIREV) . . . . . . . . . . . 20
5.0
DP83850C Applications . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
MII Interface Connections . . . . . . . . . . . . . . . . . . 21
5.2
Repeater ID Interface . . . . . . . . . . . . . . . . . . . . . 21
5.3
Inter Repeater Bus Connections . . . . . . . . . . . . 21
5.4
DP83856 100RIB Connections . . . . . . . . . . . . . . 25
5.5
Port Partition and Jabber Status LEDs . . . . . . . . 26
6.0
A.C. and D.C. Specifications . . . . . . . . . . . . . . . . . . . 27
6.1
D.C. Specifications . . . . . . . . . . . . . . . . . . . . . . . 27
6.2
A.C. Specifications . . . . . . . . . . . . . . . . . . . . . . . 28
7.0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 37
4
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1.0 Pin Connection Diagram
Order Number DP83850CVF
NS Package Number VF132A
DP83850CVF
100 Mb/s
TX/T4
Repeater Interface Controller
(100RIC)
132 pin PQFP
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
GND
VCC
TXD3
TXD2
TXD1
TXD0
TX_ER
GND
VCC
IRD_CK
IRD0
IRD1
IRD2
IRD3
/IRD_V
GND
VCC
GND
VCC
MD3
MD2
MD1
MD0
GND
VCC
IR_VECT4
IR_VECT3
IR_VECT2
IR_VECT1
IR_VECT0
/IR_COL_IN
/IR_COL_OUT
/IR_ACTIVE
IRD_ODIR
/IRD_ER
RSM3/RXECONFIG
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
RXC
GND
VCC
CRS0
CRS1
CRS2
CRS3
CRS4
CRS5
CRS6
CRS7
CRS8
CRS9
CRS10
CRS11
RXE0
RXE1
RXE2
RXE3
GND
VCC
RXE4
RXE5
RXE6
PART5
GND
VCC
PART4
PART3
PART2
PART1
PART0
RID_ER
VCC
RID3
RID2
RID1
RID0
LCK
GND
VCC
/RST
BRDC
GRDIO
RDC
RDIO
RDIR
/SDV
/ACTIVE0
GND
VCC
/IR_BUS_EN
/M_ER
M_CK
/M_DV
RXE7
RXE8
RXE9
RXE10
RXE11
GND
VCC
TXE1
TXE2
TXE3
TXE4
TXE5
TXE6
TXE7
GND
VCC
TXE8
TXE9
TXE10
TXE11
RSM0
RSM1
RSM2
TX_RDY
GND
VCC
EE_CS
EE_SK
EE_DO
EE_DI
MODE0
MODE1
TXE0
RID4
GND
1.0 Pin Connection Diagram
(Continued)
5
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1.1 Pin Table
Pin Name
Pin No.
Section
/ACTIVEO
110
2.2
/IR_ACTIVE
132
2.2
/IR_BUS_EN
113
2.2
/IR_COL_IN
130
2.2
/IR_COL_OUT
131
2.2
/IRD_ER
19
2.2
/IRD_V
15
2.2
/M_DV
116
2.2
/M_ER
114
2.2
/RST
103
2.4
/SDV
109
2.2
BRDC
104
2.4
CRS[11:0]
41-30
2.1
EE_CK
79
2.3
EE_CS
78
2.3
EE_DI
81
2.3
EE_DO
80
2.3
GND
1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123
N/A
GRDIO
105
2.4
IR_VECT[4:0]
125-129
2.2
IRD[3:0]
14-11
2.2
IRD_CK
10
2.2
IRD_ODIR
18
2.4
LCK
100
2.4
M_CK
115
2.2
MD[3:0]
119-122
2.2
MODE[1:0]
83-82
2.4
PART[5:0]
84, 87-91
2.4
RDC
106
2.2
RDIO
107
2.2
RDIR
108
2.4
RID[4:0]
93, 96-99
2.4
RID_ER
92
2.4
RSM[2:0]
74-72
2.4
RSM[3]/ RXECONFIG
20
2.4
RX_DV
25
2.1
RX_ER
26
2.1
RXC
27
2.1
RXD[3:0]
24-21
2.1
RXE[11:0]
55-48, 45-42
2.1
TX_ER
7
2.1
TX_RDY
75
2.1
TXD[3:0]
3-6
2.1
TXE[11:0]
71-68, 65-58
2.1
VCC
2, 9, 17, 29, 47, 57, 67, 77, 86, 95, 102, 112, 118, 124
N/A
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