2004 National Semiconductor Corporation
www.national.com
D
P
8
3
8
65
Gig P
H
Y
T
ER
V
10
/10
0
/
100
0 E
t
he
rnet
P
h
ysi
cal
Lay
e
r
October 2004
General Description
The DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor's South
Portland, Maine facility.
The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Twisted Pair media via an external transformer. This device
interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII), the
IEEE 802.3z Gigabit Media Independent Interface (GMII),
or Reduced GMII (RGMII).
The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor-
mance ensures drop-in replacement of existing
10/100 Mbps equipment with ten to one hundred times the
performance using the existing networking infrastructure.
Applications
The DP83865 fits applications in:
10/100/1000 Mb/s capable node cards
Switches with 10/100/1000 Mb/s capable ports
High speed uplink ports (backbone)
Features
Ultra low power consumption typically 1.1 watt
Fully compliant with IEEE 802.3 10BASE-T, 100BASE-
TX and 1000BASE-T specifications
Integrated PMD sublayer featuring adaptive equalization
and baseline wander compensation according to ANSI
X3.T12
3.3 V or 2.5 V MAC interfaces:
IEEE 802.3u MII
IEEE 802.3z GMII
RGMII version 1.3
User programmable GMII pin ordering
IEEE 802.3u Auto-Negotiation and Parallel Detection
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,
and 10 Mb/s full duplex and half duplex devices
Speed Fallback mode to achieve quality link
Cable length estimator
LED support for activity, full / half duplex, link1000,
link100 and link10, user programmable (manual on/off),
or reduced LED mode
Supports 25 MHz operation with crystal or oscillator.
Requires only two power supplies, 1.8 V (core and
analog) and 2.5 V (analog and I/O). 3.3V is supported
as an alternative supply for I/O voltage
User programable interrupt
Supports Auto-MDIX at 10, 100 and 1000 Mb/s
Supports JTAG (IEEE1149.1)
128-pin PQFP package (14mm x 20mm)
SYSTEM DIAGRAM
MAGNET
I
C
S
DP83865
10/100/1000 Mb/s
ETHERNET PHYSICAL LAYER
25 MHz
crystal or oscillator
STATUS
LEDs
DP83820
10/100/1000 Mb/s
ETHERNET MAC
MII
GMII
RGMII
10BASE-T
100BASE-TX
1000BASE-T
RJ
-
4
5
DP83865 Gig PHYTER
V
10/100/1000 Ethernet Physical Layer
PHYTER is a registered trademark of National Semiconductor Corporation
3
www.national.com
Table of Contents
1.0
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
MAC Interfaces (MII, GMII, and RGMII) . . . . . . . 5
1.2
Management Interface . . . . . . . . . . . . . . . . . . . . 7
1.3
Media Dependent Interface . . . . . . . . . . . . . . . . 7
1.4
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6
Device Configuration and LED Interface . . . . . . . . 8
1.7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . 11
1.9
Special Connect Pins . . . . . . . . . . . . . . . . . . . . 11
1.10
Pin Assignments in the Pin Number Order . . . . 12
2.0
Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1
Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 18
2.2
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
Register Description . . . . . . . . . . . . . . . . . . . . . . 21
3.0
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1
Accessing Expanded Memory Space . . . . . . . . . 40
3.2
Manual Configuration . . . . . . . . . . . . . . . . . . . . . . 40
3.3
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4
Auto-Negotiation Register Set . . . . . . . . . . . . . . . 44
3.5
Auto-MDIX resolution . . . . . . . . . . . . . . . . . . . . . . 44
3.6
Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7
PHY Address, Strapping Options and LEDs . . . . 45
3.8
Reduced LED Mode . . . . . . . . . . . . . . . . . . . . . . 45
3.9
Modulate LED on Error . . . . . . . . . . . . . . . . . . . . 45
3.10
MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11
Clock to MAC Enable . . . . . . . . . . . . . . . . . . . . . . 46
3.12
MII/GMII/RGMII Isolate Mode . . . . . . . . . . . . . . . 46
3.13
Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.14
IEEE 802.3ab Test Modes . . . . . . . . . . . . . . . . . . 46
3.15
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.16
Low Power Mode / WOL . . . . . . . . . . . . . . . . . . . 47
3.17
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 47
3.18
BIST Configuration . . . . . . . . . . . . . . . . . . . . . . . 47
3.19
Cable Length Indicator . . . . . . . . . . . . . . . . . . . . . 48
3.20
10BASE-T Half Duplex Loopback . . . . . . . . . . . . 48
3.21
I/O Voltage Selection . . . . . . . . . . . . . . . . . . . . . . 48
3.22
Non-compliant inter-operability mode . . . . . . . . . 48
4.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1
1000BASE-T PCS Transmitter . . . . . . . . . . . . . . 49
4.2
1000BASE-T PMA Transmitter . . . . . . . . . . . . . . 50
4.3
1000BASE-T PMA Receiver . . . . . . . . . . . . . . . . 50
4.4
1000BASE-T PCS Receiver . . . . . . . . . . . . . . . . 51
4.5
Gigabit MII (GMII) . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6
Reduced GMII (RGMII) . . . . . . . . . . . . . . . . . . . . 53
4.7
10BASE-T and 100BASE-TX Transmitter . . . . . . 54
4.8
10BASE-T and 100BASE-TX Receiver . . . . . . . . 57
4.9
Media Independent Interface (MII) . . . . . . . . . . . . 60
5.0
Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3
Power Supply Decoupling . . . . . . . . . . . . . . . . . . 64
5.4
Sensitive Supply Pins . . . . . . . . . . . . . . . . . . . . . 64
5.5
PCB Layer Stacking . . . . . . . . . . . . . . . . . . . . . . . 64
5.6
Layout Notes on MAC Interface . . . . . . . . . . . . . . 66
5.7
Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . 66
5.8
RJ-45 Connections . . . . . . . . . . . . . . . . . . . . . . . 67
5.9
LED/Strapping Option . . . . . . . . . . . . . . . . . . . . . 67
5.10
Unused Pins and Reserved Pins . . . . . . . . . . . . . 67
5.11
I/O Voltage Considerations . . . . . . . . . . . . . . . . . 68
5.12
Power-up Recommendations . . . . . . . . . . . . . . . 68
5.13
Component Selection . . . . . . . . . . . . . . . . . . . . . 68
6.0
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 71
6.1
DC Electrical Specification . . . . . . . . . . . . . . . . . 71
6.2
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4
1000 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5
RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6
100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.7
10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.8
Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . 79
6.9
Serial Management Interface Timing . . . . . . . . . 80
6.10
Power Consumption . . . . . . . . . . . . . . . . . . . . . . 81
7.0
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . 82
7.1
Do I need to access any MDIO register to start up
the PHY? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2
I am trying to access the registers through MDIO
and I got invalid data. What should I do? . . . . . 82
7.3
Why can the PHY establish a valid link but can
not transmit or receive data? . . . . . . . . . . . . . . . 82
7.4
What is the difference between TX_CLK,
TX_TCLK, and GTX_CLK? . . . . . . . . . . . . . . . . 82
7.5
What happens to the TX_CLK during 1000 Mbps
operation? Similarly what happens to RXD[4:7]
during 10/100 Mbps operation? . . . . . . . . . . . . . 82
7.6
What happens to the TX_CLK and RX_CLK
during Auto-Negotiation and during idles? . . . . . 82
7.7
Why doesn't the Gig PHYTER V complete Auto-
Negotiation if the link partner is a forced
1000 Mbps PHY? . . . . . . . . . . . . . . . . . . . . . . . . 82
7.8
What determines Master/Slave mode when Auto-
Negotiation is disabled in 1000Base-T mode? . . 82
7.9
How long does Auto-Negotiation take? . . . . . . . 83
7.10
How do I measure FLP's? . . . . . . . . . . . . . . . . . 83
7.11
I have forced 10 Mbps or 100 Mbps operation but
the associated speed LED doesn't come on. . . . 83
7.12
I know I have good link, but register 0x01, bit 2
"Link Status" doesn't contain value `1' indicating
good link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.13
Your reference design shows pull-up or pull-down
resistors attached to certain pins, which conflict
with the pull-up or pull-down information specified
in the datasheet? . . . . . . . . . . . . . . . . . . . . . . . . 83
7.14
How is the maximum package case temperature
calculated? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.15
The DP83865 will establish Link in 100 Mbps
mode with a Broadcom part, but it will not
establish link in 1000 Mbps mode. When this
happens the DP83865's Link LED will blink on
and off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.16
How do I quickly determine the quality of the
link over the cable ? . . . . . . . . . . . . . . . . . . . . . . 83
7.17
What is the power up sequence for DP83865? . 83
7.18
What are some other applicable documents? . . 84
8.0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 86
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