TL F 11157
DP83902A
ST-NIC
Serial
Network
Interface
Controller
for
Twisted
Pair
PRELIMINARY
November 1995
DP83902A ST-NIC
TM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA CD local area net-
works These include Ethernet (10BASE5) Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T) The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface
and 10BASE-T transceiver functions in accordance with the
IEEE 802 3 standards
The DP83902A's 10BASE-T transceiver fully complies with
the IEEE standard This functional block incorporates the
receiver transmitter collision heartbeat loopback jabber
and link integrity blocks as defined in the standard The
transceiver when combined with equalization resistors
transmit receive filters and pulse transformers provides a
complete physical interface from the DP83902A's ENDEC
module and the twisted pair medium
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit sec Also included are colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
(Continued)
Features
Y
Single chip solution for IEEE 802 3 10BASE-T
Y
Integrated controller ENDEC and transceiver
Y
Full AUI interface
Y
No external precision components required
Y
3 levels of loopback supported
Transceiver Module
Y
Integrates transceiver electronics including
Transmitter and receiver
Collision detect heartbeat and jabber timer
Link integrity test
Y
Link disable and polarity detection correction
Y
Integrated smart receive squelch
Y
Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y
10 Mb s Manchester encoding decoding plus clock re-
covery
Y
Transmitter half or full step mode
Y
Squelch on receive and collision pairs
Y
Lock time 5 bits typical
Y
Decodes Manchester data with up to
g
18 ns jitter
MAC Controller Module
Y
100% DP8390 software hardware compatible
Y
Dual 16-bit DMA channels
Y
16-byte internal FIFO
Y
Efficient buffer management implementation
Y
Independent system and network clocks
Y
Supports physical multicast and broadcast address fil-
tering
Y
Network statistics storage
1 0 System Diagram
Station or DTE
TL F 11157 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
ST-NIC
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
General Description
(Continued)
The Media Access Control function which is provided by the
Network Interface Control module (NIC) provides simple
and efficient packet transmission and reception control by
means of unique dual DMA channels and an internal FIFO
Bus arbitration and memory control logic are integrated to
reduce board cost and area overheads
DP83902A provides a comprehensive single chip solution
for 10BASE-T IEEE 802 3 networks and is designed for
easy interface to other transceivers via the AUI interface
Due to the inherent constraints of CMOS processing isola-
tion is required at the AUI differential signal interface for
10BASE5 and 10BASE2 applications Capacitive or induc-
tive isolation may be used
Table Of Contents
1 0 SYSTEM DIAGRAM
2 0 PIN DESCRIPTION
3 0 BLOCK DIAGRAM
4 0 FUNCTIONAL DESCRIPTION
5 0 TRANSMIT RECEIVE PACKET
ENCAPSULATION DECAPSULATION
6 0 DIRECT MEMORY ACCESS CONTROL (DMA)
7 0 PACKET RECEPTION
8 0 PACKET TRANSMISSION
9 0 REMOTE DMA
10 0 INTERNAL REGISTERS
11 0 INITIALIZATION PROCEDURES
12 0 LOOPBACK DIAGNOSTICS
13 0 BUS ARBITRATION AND TIMING
14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS
15 0 SWITCHING CHARACTERISTICS
16 0 AC TIMING TEST CONDITIONS
17 0 PHYSICAL DIMENSIONS
Connection Diagrams
TL F 11157 2
Order Number DP83902AV
See NS Package Number V84A
2
Connection Diagrams
(Continued)
TL F 11157 56
Order Number DP83902AVLJ
See NS Package Number VLJ100A
3
Connection Diagrams
(Continued)
TL F 11157 65
Order Number DP83902AVJG
See NS Package Number VJG100A
2 0 Pin Description
PQFP
PLCC
AVJG
Pin
I O
Description
Pin No
Pin No
Pin No
Name
BUS INTERFACE PINS
95
5
92
INT
O
INTERRUPT
Indicates that the DP83902A requires CPU attention after
reception transmission or completion of DMA transfers The interrupt is cleared
by writing to the ISR (Interrupt Status Register) All interrupts are maskable
96
6
93
WACK
I
WRITE ACKNOWLEDGE
Issued from system to DP83902A to indicate that
data has been written to the external latch The DP83902A will begin a write
cycle to place the data in local memory
98
7
95
PRD
O
PORT READ
Enables data from external latch on to local bus during a
memory write cycle to local memory (remote write operation) This allows
asynchronous transfer of data from the system memory to local memory
99 100
8 11
96
RA3 RA0
I
REGISTER ADDRESS
These four pins are used to select a register to be read
1 2
98 100
or written The state of these inputs is ignored when the DP83902A is not in
slave mode (CS high)
4
2 0 Pin Description
(Continued)
PQFP
PLCC
AVJG
Pin
I O
Description
Pin No
Pin No
Pin No
Name
BUS INTERFACE PINS
(Continued)
4 8
12 23
2 4 6
AD0
I O Z
MULTIPLEXED ADDRESS DATA BUS
10 12
28 31
7 9 15
AD15
Register Access with DMA inactive CS low and ACK returned from
14 15 17
20 23
DP83902A pins AD0AD7 are used to read and write register data AD8
18 22 23
AD15 float during I O transfers SRD SWR pins are used to select
25 26
direction of transfer
Bus Master with BACK input asserted
During t1 of memory cycle AD0 AD15 contain address
During t2 t3 t4 AD0 AD15 contain data (word transfer mode)
During t2 t3 t4 AD0AD7 contain data AD8AD15 contain address (byte
transfer mode)
Direction of transfer is indicated by DP83902A on MWR MRD lines
27
32
25
ADS0
I O Z
ADDRESS STROBE 0
Input with DMA inactive and CS low latches RA0RA3 inputs on falling
edge If high data present on RA0RA3 will flow through latch
Output When Bus Master latches address bits (AD0AD15) to external
memory during DMA transfers
28
33
26
CS
I
CHIP SELECT
Chip Select places controller in slave mode for mP access to
internal registers Must be valid through data portion of bus cycle RA0 RA3
are used to select the internal register SWR and SRD select direction of
data transfer
29
34
27
MWR
O Z
MASTER WRITE STROBE
(Strobe for DMA transfers)
Active low during write cycles (t2 t3 tw) to buffer memory Rising edge
coincides with the presence of valid output data TRI-STATE until BACK
asserted
30
35
28
MRD
O Z
MASTER READ STROBE
(Strobe for DMA transfers)
Active during read cycles (t2 t3 tw) to buffer memory Input data must be
valid on rising edge of MRD TRI-STATE until BACK asserted
31
36
29
SWR
I
SLAVE WRITE STROBE
Strobe from CPU to write an internal register
selected by RA0 RA3 Data is latched into the DP83902A on the rising
edge of this input
32
37
30
SRD
I
SLAVE READ STROBE
Strobe from CPU to read an internal register
selected by RA0 RA3 The register data is output when SRD goes low
33
38
31
ACK
O
ACKNOWLEDGE
Active low when DP83902A grants access to CPU Used
to insert WAIT states to CPU until DP83902A is synchronized for a register
read or write operation
36
40
34
BSCK
I
BUS CLOCK
This clock is used to establish the period of the DMA memory
cycle Four clock cycles (t1 t2 t3 t4) are used per DMA cycle DMA
transfers can be extended by one BSCK increment using the READY input
37
41
35
RACK
I
READ ACKNOWLEDGE
Indicates that the system DMA or host CPU has
read the data placed in the external latch by the DP83902A The DP83902A
will begin a read cycle to update the latch
39
42
36
PWR
O
PORT WRITE
Strobe used to latch data from the DP83902A into external
latch for transfer to host memory during Remote Read transfers The rising
edge of PWR coincides with the presence of valid data on the local bus
41
43
37
READY
I
READY
This pin is set high to insert wait states during a DMA transfer The
DP83902A will sample this signal at t3 during DMA transfers
42
44
39
PRQ
O Z
PORT REQUEST ADDRESS STROBE 1
ADS1
32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 A31 into
external latches (A16 A31 are the fixed addresses stored in RSAR0
RSAR1) ADS1 will remain at TRI-STATE until BACK is received
16-BIT MODE If LAS is not set in the Data Configuration Register this
line is programmed as PRQ and is used for Remote DMA Transfers The
DP83902A initiates a single remote DMA read or write operation by
asserting this pin In this mode PRQ will be a standard logic output
Note
This line will power up as TRI-STATE until the Data Configuration Register is programmed
5
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